Memory Devices

Computer System
 Memory Devices
Flip-Flop: electronic memory device
Register: group of FFs, high speed,
extensively used in the internal operation of a computer
IC memory array
Capacitor: data are stored as charge of capacitor
Main memory: semoconductor memory (RAM, ROM)
It is very fast in operation but volatile
It is in constant communication with CPU (working memory)
Auxiliary memory : mass storage (Magnetic disk and CD)
It can keep storage without power.
It operates at slower speed
Stores data that are not currently being used by CPU
Memory Terminologies
 Memory Terminologies

Capacity : A way of specifying how many bits can be stored

in a memory device
Density: bits/area
 Memory Terminologies
Address: A number that identifies the location of a word in
memory. Each word stored in a memory device or system has
a unique address.
 Memory Terminologies
Read Operation: The operation whereby the binary word
stored in a specific memory location (address) is sensed and
then transferred to another device. For example, if we want
to use word 4 of the memory for some purpose, we must
perform a read operation on address 100. The read
operation is often called a fetch operation because a word is
being fetched from memory.
Write Operation: The operation whereby a new word is
placed into a particular memory location. It is also referred
to as a store operation.
Whenever a new word is written into a memory location, it
replaces the word that was previously stored there.
 Memory Terminologies

Access Time: A measure of a memory device’s operating

speed. It is the amount of time required to perform a read
operation. It is the time between the memory receiving a
new address input and the data becoming available at the
memory output. The symbol tACC is used for access time.
Volatile Memory: Any type of memory that requires the
application of electrical power in order to store information.
If the electrical power is removed, all information stored in
the memory will be lost.
 Memory Terminologies

Random-Access Memory (RAM): Memory in which the actual

physical location of a memory word has no effect on how long
it takes to read from or write into that location. Access time is
the same for any address in memory. Most semiconductor
memories are RAMs.
Sequential-Access Memory (SAM): A type of memory in
which the access time is not constant but varies depending on
the address location. A particular stored word is found by
sequencing through all address locations until the desired
address is reached. This produces access times that are much
longer than those of RAMs. (example:magnetic tape backup).
 Memory Terminologies
Read/Write Memory (RWM): Any memory that can be read
from or written into with equal ease.
Read-Only Memory (ROM): A broad class of semiconductor
memories designed for applications where the ratio of read
operations to write operations is very high. A ROM can be
written into only once, and this operation is normally
performed at the factory. Other types of ROM are actually
read-mostly memories (RMM), which can be written into
more than once; but the write operation is more complicated
than the read operation, and it is not performed very often.
All ROM is nonvolatile.
 Memory Terminologies

Static Memory Devices: Semiconductor memory devices in

which the stored data will remain permanently stored as long
as power is applied, without the need for periodically
rewriting the data into memory.
Dynamic Memory Devices: Semiconductor memory devices
in which the stored data will not remain permanently stored,
even with power applied,unless the data are periodically
rewritten into memory. The latter operation is called a refresh
operation.
 General Memory Operation
Every memory system requires several different types of input
and output lines to perform the following functions:

1. Select the address in memory that is being accessed for a

read or write operation.
2. Select either a read or a write operation to be performed.
3. Supply the input data to be stored in memory during a
write operation.
4. Hold the output data coming from memory during a read
operation.
5. Enable (or disable) the memory so that it will (or will not)
respond to the address inputs and read/write command.
Memory Diagram
Read & Write Operations
Problems
CPU-Memory Connection
Write Operation
Read Operation
Bus
Typical ROM Block
Typical ROM Table
ROM Architecture
 ROM Architecture

Register Array
Address Decoder
Output Buffer
ROM Timing
 Types of ROM

1. Mask Programmed ROM (MROM)

2. Programmable ROM (PROM)
3. Erasable Programmable ROM (EPROM)
4. Electrically Erasable Programmable ROM (EEPROM)
5. CD-ROM
MROM
MROM
 PROM
• A mask-programmable ROM is very expensive and would
not be used except in high-volume applications,
• For lower-volume applications, manufacturers have
developed fusiblelink PROMs that are user-programmable;
• Once programmed, a PROM is like an MROM , if the
program in the PROM is faulty , the PROM must be thrown
away.
• So, these devices are referred to as “one-time
programmable” (OTP) ROMs.
• The fusible-link PROM structure is very similar to the MROM
structure
 PROM

• A PROM comes from the manufacturer with a thin, fuse link

connection in the source leg of every transistor.
• In this condition, every transistor stores a 1.
• The user can then “blow”the fuse for any transistor that
needs to store a 0.
• Typically, data can be programmed or “burned into” a PROM
by selecting a row by applying the desired address to the
address inputs, placing the desired data on data pins, and
then applying a pulse to a special programming pin on IC.
PROM
 EPROM
• An EPROM can be programmed by the user, and it can also be erased
and reprogrammed as often as desired.
• Once programmed, the EPROM is a nonvolatile.
• The process for programming an EPROM is the same as that for a
PROM.
• The storage element of an EPROM is a MOS transistor with a floating
silicon gate
• To program a 0, a high-voltage pulse is used to leave a net charge on
the floating gate.
• The data are erased by restoring all cells to a logic 1. To do this, the
charge on the floating electrode is neutralized by exposing the silicon
to high-intensity ultraviolet (UV) light for several minutes.
• It uses quartz “window,” which allows the UV light to enter.
EPROM
 EPROM

A clean EPROM can be programmed in less than a minute

once the desired data have been entered, transferred, or
downloaded into the EPROM programmer.

The major disadvantages of UVEPROMs :

1. They must be removed from the circuit to be programmed

and erased,
2. The erase operation erases the entire chip.
 EEPROM
• Disadvantages of EPROM were overcome by EEPROM.
• The EEPROM retains the same floating-gate structure as the EPROM,
but with the addition of a very thin oxide region above the drain of the
MOSFET memory cell.
• This modification produces its electrical erasability by applying a high
voltage (21 V) between the MOSFET’s gate and drain.
• The erasing and programming of an EEPROM can be done in circuit
(without a UV light source and a special PROM programmer unit).
• EEPROM has ability to erase and rewrite individual bytes in the
memory array electrically.
• During a write operation, internal circuitry automatically erases all of
the cells at an address location prior to writing in the new data.
 EEPROM

• The byte erasability of the EEPROM and its high level of

integration come with two penalties: density and cost.
• The memory cell complexity and the on-chip support
circuitry place EEPROMs far behind an EPROM in bit
capacity per square millimeter of silicon.
• A 1-Mbit EEPROM requires about twice as much silicon as a
1-Mbit EPROM.
• So despite its operational superiority, the EEPROM’s
shortcomings in density and cost-effectiveness have kept it
from replacing the EPROM.
 CD-ROM
A very prominent type of storage is the compact disk (CD).
Format of the data is different.
Disks are manufactured with a highly reflective surface.
To store data on the disks, a very intense laser beam is focused on a very
small point on the disk.
This beam burns a light-diffracting pit at that point on the disk surface.
Digital data (1s and 0s) are stored on the disk one bit at a time by
burning or not burning a pit into the reflective coating.
The digital information is arranged on the disk as a continuous spiral of
data points.
The precision of the laser beam allows very large quantities of data to
be stored on a small disk.
 CD-ROM
• In order to read the data, a much less powerful laser beam is focused
onto the surface of the disk.
• At any point, the reflected light is sensed as either a 1 or a 0.
• This optical system is mounted on a mechanical carriage that moves
back and forth along the radius of the disk.
• The data retrieved from the optical system come one bit at a time in a
serial data stream.
• If the disk is being used for audio recording, this stream of data is
converted into an analog waveform.
• If the disk is being used as ROM, the data are decoded into parallel
bytes that the computer can use.
• It is very sophisticated, relatively inexpensive. and is becoming a
standard way of loading large amounts of data into a PC.
Data retrieval from CD-ROM
 Flash Memory

• The challenge for semiconductor engineers was to fabricate a

nonvolatile memory with the EEPROM’s in-circuit electrical erasability,
but with densities and costs much closer to those of EPROMs, while
retaining the high-speed read access of both. The response to this
challenge was the flash memory.
• Structurally, a flash memory cell is like the simple single-transistor
• EPROM cell (and unlike the more complex two-transistor EEPROM
cell), being only slightly larger.
• It has a thinner gate-oxide layer that allows electrical erasability but
can be built with much higher densities than EEPROMs.
• The cost of flash memory is considerably less than for EEPROM..
 Flash Memory

• Flash memories are so called because of their rapid erase and write
times.
• Most flash chips use a bulk erase operation in which all cells on the
chip are erased simultaneously; this bulk erase process requires
hundreds of ms compared to 20 minutes for UV EPROMs.
• Some newer flash memories offer a sector erase mode, where specific
sectors of the memory array can be erased at one time. This prevents
having to erase and reprogram all cells when only a portion of the
memory needs to be updated.
• A typical flash memory has a write time of 10 ms per byte compared to
100 for the most advanced EPROM and 5 ms for EEPROM.
Complexity & Cost
RAM Architecture
 RAM
Types of RAM: There are two types of RAM.

1) Static RAM: This type of RAM can store data as long as

power is applied to the chip without the need for
periodically rewriting the data into memory. These are
constructed using Flip-Flops.
2) Dynamic RAM:
Static RAM
 SRAM
1. SRAM is static. SRAM does not need to be refreshed as
the transistors inside would continue to hold the data as
long as the power supply is not cut off.
2. SRAM is faster compared to DRAM
3. SRAM consumes less power than DRAM
4. SRAM uses more transistors per bit of memory,
5. SRAM requires more space
6. SRAM is more expensive.
7. SRAM is commonly used in cache memory.
SRAM IC
 DRAM
1. DRAM is dynamic DRAM requires the data to be
refreshed periodically in order to retain the data.
2. DRAM is slower
3. DRAM consumes more power than SRAM
4. A DRAM module only needs a transistor and a capacitor
for every bit of data.
5. A DRAM module can have 4 times more capacity to an
SRAM module.
6. DRAM is less expensive than SRAM
7. Extra circuitry are needed for refreshing.
8. Cheaper DRAM is used in main memory.
DRAM structure
 DRAM cell
The switches SW1 through SW4 are actually MOSFETs that are
controlled by various address decoder outputs and the signal.
The capacitor is the actual storage cell.
One sense amplifier would serve an entire column of memory
cells, but operate only on the bit in the selected row.
 DRAM writing
• To write data to the cell, signals from the address decoding
and read/write logic will close switches SW1 and SW2, while

keeping SW3 and SW4 open.

• This connects the input data to C.
• A logic 1 at the input charges C, and a logic 0 discharges it.
• Then the switches are open so that C is disconnected from
the rest of the circuit. Ideally, C would retain its charge
indefinitely, but there is always some leakage path through
the off switches, so that C will gradually lose its charge.
 DRAM reading

• To read data from the cell, switches SW2, SW3, and SW4 are
closed, and SW1 is kept open.
• This connects the stored capacitor voltage to the sense
amplifier. The sense amplifier compares the voltage with
some reference value to determine if it is a logic 0 or 1, and
it produces a solid 0 V or 5 V for the data output.
• This data output is also connected to C (SW2 and SW4 are
closed) and refreshes the capacitor voltage by recharging or
discharging. In other words, the data bit in a memory cell is
refreshed each time it is read.
 DRAM Refreshing
• Each DRAM memory cell must be refreshed periodically
(typically, every 4 to 16 ms, depending on the device) or its
data will be lost.
• This requirement would appear to be extremely difficult.
For example, a 1M * 1 DRAM has 1020 = 1,048,576 cells.
• To ensure that each cell is refreshed within 4 ms, it would
require that read operations be performed on successive
addresses at the rate of one every 4 ns.
• Fortunately, manufacturers have designed DRAM chips so
that whenever a read operation is performed on a cell, all
of the cells in that row will be refreshed.
 DRAM Refreshing
• It is necessary to do a read operation only on each row of a
DRAM array once every 4 ms to guarantee that each cell of
the array is refreshed.
• However, during the normal operation of the system in
which a DRAM is functioning, it is unlikely that a read
operation will be performed on each row of the DRAM
within the required refresh time limit.
• Therefore, some kind of refresh control logic is needed
either external to the DRAM chip or as part of its internal
circuitry.
 DRAM Refreshing
• There are two refresh modes: a burst refresh and a
distributed refresh.
• In a burst refresh mode, the normal memory operation is
suspended, and each row of the DRAM is refreshed in
succession until all rows have been refreshed.
• In a distributed refresh mode, the row refreshing is
interspersed with the normal operations of the memory.
• A special chip called DRAM Controller is used now.
 Types of DRAM

FPM DRAM: First Page mode DRAM

EDO DRAM: Extended data output DRAM
SDRAM : Synchronous DRAM
DDRSDRAM : Double data rate SDRAM
SLDRAM : Synchronous Link DRAM
DRDRAM : Direct Rambus DRAM
Expanding word size
 Expanding word size and capacity

The 2125A is a static-RAM IC that has a capacity of 1K × 1, one

active-LOW chip select input, and separate data input and
output. Show how to combine several 2125A ICs to form a
1K × 8 module.
We want to combine several 2K × 8 PROMs to produce a total
capacity of 8K × 8. How many PROM chips are needed? How
many address bus lines are required?

What would be needed to expand the memory of Figure 12-

37 to 32K × 8? Describe what address lines are used.
Expanding word size
Expanding Capacity
Expanding Capacity