National Taiwan University

Verilog HDL Overview

Prof. An-Yeu Wu

Date:2002/05/17
For NTUEE Undergraduate
VLSI Design Course
OUTLINE
Introduction
Basics of the Verilog Language
Gate-level modeling
Data-flow modeling
Behavioral modeling
Simulation and test bench

A. Y. Wu pp. 2
What is Verilog HDL ?
Hardware Description Language
Mixed level modeling
Behavioral
—Algorithmic ( like high level language)
—Register transfer (Synthesizable)
Structural
—Gate (AND, OR ……)
—Switch (PMOS, NOMS, JFET ……)
Single language for design and simulation
Built-in primitives and logic functions
User-defined primitives
Built-in data types
High-level programming constructs

A. Y. Wu pp. 3
OUTLINE
Introduction
Basics of the Verilog Language
Overview of Verilog Module
Identifier & Keywords
Logic Values
Data Types
Numbers & Negative Numbers
Gate-level modeling
Data-flow modeling
Behavioral modeling
Simulation and test bench

A. Y. Wu pp. 4
Overview of Verilog Module

Test bench
A. Y. Wu pp. 5
Basic unit --Module
module module_name (port_name);
port declaration
data type declaration
module functionality or structure
endmodule

A. Y. Wu pp. 6
Latch
module Latch ( Q,Q_b,D,D_b,clk );
//port declaration
output Q,Q_b;
input D,D_b,clk ;
reg Q,Q_b; Q=D․clk+ clk_b․Q
always@(D or D_b or clk or Q_b=D_b․clk+clk_b․Q_b
Q_b or Q)
D
begin Q
Q=(D&clk)|(~clk&Q);
Q_b=D_b&clk|~clk&Q_b; clk
end
Q_b
D_b
endmodule

A. Y. Wu pp. 7
Register / Flip-flop
module D_register(q,d1,clk);
Sub-module
input d1,clk;
output q; Q

wire d1_b, clk_b;

assign d1_b=~d1; clk

assign clk_b=~clk;
dff dff1(d,d_b,d1,d1_b,clk_b),
dff ( Q,Q_b,D,D_b,clk );
dff2(q_b,q,d_b,d,clk);

endmodule

A. Y. Wu pp. 8
Instances
module adder (in1,in2,cin,sum,cout);
.......
endmodule

module adder8(....) ; Mapping port positions

adder add1(a,b,1’b0,s1,c1) ,
add2(.in1(a2),.in2(b2),.cin(c1),.sum(s2)
,.cout(c2)) ; Mapping names
.....
endmodule
A. Y. Wu pp. 9
Identifier & Keywords
Identifier
User-provided names for Verilog objects in the
descriptions
Legal characters are “a-z”, “A-Z”, “0-9”, “_”, and “$”
First character has to be a letter or an “_”
—Example: Count, _R2D2, FIVE$
Keywords
Predefined identifiers to define the language
constructs
All keywords are defined in lower case
Cannot be used as identifiers
—Example:initial, assign, module, always….

A. Y. Wu pp. 10
Logic Values
0:logic 0 / false
1:logic 1 / true
X:unknown logic value
Z:high-impedance

A. Y. Wu pp. 11
Data Types
Nets ( wire or reg (in combinational always
block)
Connects between structural elements
Must be continuously driven by
—Continuous assignment (assign)
—Module or gate instantiation (output ports)
Default initial value for a wire is “Z”
Registers ( reg (in sequential always block) )
Represent abstract data storage elements
Updated at an edge trigger event and holds its
value until another edge trigger event happens
Default initial value for a wire is “X”
A. Y. Wu pp. 12
 Examples
reg a; // a scalar register
wand w; // a scalar net of type “wire and”
reg [3:0] v; // a 4-bit vector register/wire from msb to lsb
reg [7:0] m, n; // two 8-bit registers/wire
tri [15:0] busa; // a 16-bit tri-state bus

wire [0:31] w1, w2;

A. Y. Wu pp. 13
Net Types
The most common and important net types
wire and tri
—for standard interconnection wires
supply 1 and supply 0
Other wire types
wand, wor, triand, and trior
—for multiple drivers that are wired-anded and wired-ored
tri0 and tri1
—pull down and pull up
trireg
—for net with capacitive storage
—If all drivers at z, previous value is retained

A. Y. Wu pp. 14
Register Types
reg
any size, unsigned
Integer (not synthesizable)
integet a,b; // declaration
32-bit signed (2’s complement)
Time (not synthesizable)
64-bit unsigned, behaves like a 64-bit reg
$display(“At %t, value=%d”,$time,val_now)
real, realtime (not synthesizable)
real c,d; //declaration
64-bit real number
Defaults to an initial value of 0

A. Y. Wu pp. 15
Numbers & Negative Numbers
Constant numbers are integer or real
constants. Integer constants are written as
“width ‘radix value”
The radix indicates the type of number
Decimal (d or D)
Hex (h or H)
Octal (o or O)
Binary (b or B)
A number may be sized (two’s complement)
or unsized
Ex: h12_unsized = ‘h12; h12_sized = 6’h12;
Ex: PA = -12, PB = -’D12, PC= -32’D12;

A. Y. Wu pp. 16
Operators

A. Y. Wu pp. 17
Example
assign A1 = (3+2) %2;
A1 = 1
assign A2 = 4 >> 1; assign A4 = 1 >> 2;
A2 = 2 A4 = 4
assign Ax = (1= =1'bx);
assign Bx = (1'bx!=1'bz);
assign D0 = (1= =0); assign D1 = (1= =1);
assign E0 = (1= = =1'bx); E0 = 0; False
assign E1 = 4'b01xz = = = 4'b01xz; E1 = 1; True
assign F1 = (4'bxxxx = = = 4'bxxxx); F1 = 1; True
assign x = a ? b : c if (a) then x = b else x = c

A. Y. Wu pp. 18
OUTLINE
Introduction
Basics of the Verilog Language
Gate-level modeling
Data-flow modeling
Behavioral modeling
Simulation and test bench

A. Y. Wu pp. 19
Gate-level modeling(1)
The following gates are built-in types in the
simulator
and, nand, nor, or, xor, xnor
First terminal is output, followed by inputs
and a1 (out1, in1, in2);
nand a2 (out2, in21, in22, in23, in24);
buf, not
One or more outputs first, followed by one input
not N1 (OUT1, OUT2, OUT3, OUT4, INA);
buf B1 (BO1, BIN);

A. Y. Wu pp. 20
Gate-level modeling(2)
bufif0, bufif1, notif0, notif1: three-state
drivers
Output terminal first, then input, then control
bufif1 BF1 (OUTA,INA,CTRLA);
pullup, pulldown
Put 1 or 0 on all terminals
pullup PUP (PWRA, PWRB, PWRC);
Instance names are optional
ex: not (QBAR, Q)

A. Y. Wu pp. 21
Example
module MUX4x1 (Z, D0, D1,
D2, D3, S0, S1);
output Z;
input D0, D1, D2, D3, S0, S1;
and (T0, D0, S0BAR, S1BAR);
(T1, D1, S0BAR, S1),
(T2, D2, S0, S1BAR),
(T3, D3, S0, S1);
4 X 1 multiplexer circuit
not (S0BAR, S0), (S1BAR, S1);
nor (Z, T0, T1, T2, T3);
endmodule

A. Y. Wu pp. 22
OUTLINE
Introduction
Basics of the Verilog Language
Gate-level modeling
Data-flow modeling
Behavioral modeling
Simulation and test bench

A. Y. Wu pp. 23
Data-flow modeling(1)
Models behavior of combinational logic
Assign a value to a net using continuous
assignment
Examples:
wire [3:0] Z, PRESET, CLEAR;
assign Z = PRESET & CLEAR;
wire COUT, CIN;
wire [3:0] SUM, A, B;
assign {COUT, SUM} = A + B + CIN;

A. Y. Wu pp. 24
Data-flow modeling(2)
Left-hand side (target) expression can be:
Single net (ex: Z)
Part-select (ex: SUM[2:0])
Bit-select (ex: Z[1])
Concatenation of both (ex: {COUT, SUM[3:0]})
Expression on right-hand side is evaluated
whenever any operand value changes
Note: Concatenation example
{A,1’b0} -> x2
{A,2’b0} -> x4
wire [7:0]A,B; wire [16:0]C; assign C={A,B};

A. Y. Wu pp. 25
Delay
Delay between assignment of right-hand side to
left-hand side
assign #6 ASK = QUIET || LATE; //Continuous delay
Netdelay
wire #5 ARB;
// Any change to ARB is delayed 5 time units before it
takes effect
If value changes before it has a chance to
propagate, latest value change will be applied –
Inertial delay

A. Y. Wu pp. 26
OUTLINE
Introduction
Basics of the Verilog Language
Gate-level modeling
Data-flow modeling
Behavioral modeling
Simulation and test bench

A. Y. Wu pp. 27
Behavioral modeling
Procedural blocks:
initial block: executes only once
always block:executes in a loop
Block execution is triggered based on user-
specified conditions
always @ (posedge clk) ………
All procedural blocks are automatically
activated at time 0
All procedural blocks are executed
concurrently
reg is the main data type that is manipulated
within a sequential block
It holds its value until assigned a new value
A. Y. Wu pp. 28
 Initial Statement
Executes only once at the beginning of simulation
initial
statements
Used for initialization and waveform generation
//Initialization:
reg [7:0] RAM[0:1023];
reg RIB_REG;

initial begin
group integer INX;
multiple RIB_REG =0;
for (INX = 0; INX < 1024; INX = INX + 1)
statements RAM[INX] = 0;
end

A. Y. Wu pp. 29
Always Statement(1)
Executes continuously; must be used with
some form of timing control
always (timing_control) always
statements CLK = ~CLK
// Will loop indefinitely
Four forms of event expressions are often used
An OR of several identifiers (comb/seq logic)
The rising edge of a identifier (for clock signal of a
register)
The falling edge of a identifier (for clock signal of a
register)
Delay control (for waveform generator)

A. Y. Wu pp. 30
Always Statement(2)
Any number of initial and always statements
may appear within a module
Initial and always statements are all executed
in parallel

A. Y. Wu pp. 31
Example
module example (D, CURRENT_STATE, Q, NEXT_STATE);
input D, CURRENT_STATE;
output Q, NEXT_STATE;
reg CLK, Q, NEXT_STATE; delay-controlled always block
clock period = 10
always #5 CLK = ~CLK;
activated when CLK has
always @(posedge CLK)
a 0 -> 1 transition
begin
Q =D;
activated when CLK has
end
always @(negedge CLK) a 1 -> 0 transition
begin
NEXT_STATE = CURRENT_STATE;
end
endmodule

A. Y. Wu pp. 32
Procedural Assignments
The assignment statements that can be used inside
an always or initial block
The target must be a register or integer type
always @(A or B) // infer wire
begin
B = A;
C = B;
end // C=A
always @(posedge CLK) // infer flip-flop
begin
B <= A;
C <= B;
D <= C;
end // Clock skew!!

A. Y. Wu pp. 33
Conditional Statements
if and else if statements
case statement
if (expression)
case (case_expression)
statements
case_item_expression
{ else if (expression)
{, case_item_expression }:
statements }
statements
[ else
statements ] ……
[ default: statements ]
if (total < 60) begin endcase
grade = C;
total_C = total_C + 1; case (OP_CODE)
end 2`b10: Z = A + B;
else if (sum < 75) begin 2`b11: Z = A – B;
grade = B; 2`b01: Z = A * B;
total_B = total_B + 1; 2`b00: Z = A / B;
end default: Z = 2`bx;
else grade = A; endcase

A. Y. Wu pp. 34
Loop Statements
Four loop statements are supported
The for loop
The while loop
The repeat loop
The forever loop
The syntax of loop statements is very similar to
that in C language
Most of the loop statements are not synthe-
sizable in current commercial synthesizers

A. Y. Wu pp. 35
OUTLINE
Introduction
Basics of the Verilog Language
Gate-level modeling
Data-flow modeling
Behavioral modeling
Simulation and test bench

A. Y. Wu pp. 36
Simulation and test bench(1)
Design, stimulus, control, saving
responses, and verification can be
completed in a single language
Stimulus and control
—Use initial procedural block
Saving responses
—Save on change
—Display data
Verification
—Automatic compares with expected responses

A. Y. Wu pp. 37
Simulation and test bench(2)
The behavior of a design can be simulated
by HDL simulators
Test benches are given by users as the inputs of the
design
Some popular simulators
—Verilog-XL (Cadence TM , direct-translate
simulator)
—NC-Verilog (Cadence TM , compiled-code
simulator)
—VCS (ViewLogic TM , compiled-code simulator)

A. Y. Wu pp. 38
Supports for Verification
Verilog provides a number of system tasks and
system functions.
$time is a system function that returns the current
simulation time.
$monitor is a system task that displays the values of
the argument list whenever any of the arguments
change.

Examples:
$monitor($time,,out,,a,,b,,sel);
$monitor($time,”%b %h %d %o,
sig1,sig2,sig3,sig4);

A. Y. Wu pp. 39
Test Bench
module test_bench;
data type declaration
module instantiation
applying stimulus
display results
endmodule

A test bench is a top level module without inputs and outputs

A. Y. Wu pp. 40
Example
module testfixture;
reg [15:0] a,b,ci;
wire [15:0] sum;
data type declaration
wire cout;

adder adder0(sum,cout,a,b,ci);
module instantiation
initial begin
a=0;b=0;ci=0;
#10 ci=1; #10 ci=0; b=1;
#10 ci=1; a=1; applying stimulus
#10 $finish;
end
Initial $monitor ($time,” sum= %b cout= %b a= %b b= %b
ci=%b”,sum,cout,a,b,ci);
display results
endmodule

A. Y. Wu pp. 41