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Switching Characteristics of CMOS

The document discusses the switching characteristics of a CMOS inverter. It defines terms like rise time, fall time, and delay time. It then presents an analytical delay model describing the two intervals that make up the fall time. The rise time is obtained through symmetry. An empirical delay model uses circuit simulation to measure values that are substituted into equations to predict delay.

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Joel D Livingstone
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826 views

Switching Characteristics of CMOS

The document discusses the switching characteristics of a CMOS inverter. It defines terms like rise time, fall time, and delay time. It then presents an analytical delay model describing the two intervals that make up the fall time. The rise time is obtained through symmetry. An empirical delay model uses circuit simulation to measure values that are substituted into equations to predict delay.

Uploaded by

Joel D Livingstone
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PPTX, PDF, TXT or read online on Scribd
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Switching Characteristics

of CMOS inverter
Switching Characteristics of
CMOS inverter
• Develop analytical delay model and empirical delay
model to describe switching characteristics

• Limitation of switching speed of CMOS gate – time


taken to charge and discharge CL due to transition at
the input followed to output
Terminologies
• Rise time tr : time for a waveform to rise from 10% to
90% of its steady state value.

• Fall time tf : time for a waveform to fall from 90% to


10% of its steady state value.

• Delay time td : time difference between 50% of input


transition and 50% of output transition.
tdf high to low delay
tdr low to high delay
Analytical Delay Model
• Fall time tf consists of two intervals

tf1 = period during which the capacitor voltage Vout


drops from 0.9 VDD to (VDD - Vtn)

tf2 = period during which the capacitor voltage Vout


drops from (VDD - Vtn) to 0.1 VDD
• Rise time tr can be obtained as same due to symmetry
of CMOS circuit

• Fall time is faster than rise time – due to different


carrier mobilities
• To have approximately same rise time and fall time
make

• Width of p-device must be increased 2 to 3 times the


width of n-device

• This in turn depends on the parameters of the process


of MOS transistor
• delay time td of a gate is dominated by the output rise
and fall time
• Average delay time is given by
Empirical Delay Model
• Circuit simulator is used to model the inverter or gate
and the measured values are back substituted into
appropriate equations

• These constants now used to predict delay values

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