Unit-1

ASM
 ASM stands for algorithmic state machine.
 Algorithm: Finite set of instructions/steps to solve a problem
 The control algorithm plays a major role in a digital design, so
we need a good notation for expressing hardware algorithms.
 The notation should assist the designer in expressing the
abstract algorithm and should support the conversion of the
algorithm into hardware.
 There are several ways of describing the control (pseudo code
and flowcharts etc ).
 Algorithmic State Machines (ASM)
Flowchart
(i) A flowchart is a way of showing actions and control flow in an
algorithm
(ii)Translates word description into a series of operations with
conditions for execution
Algorithmic State Machine (ASM)
An Algorithmic State Machine (ASM) is simply a flowchart-like way to
specify state diagrams for sequential logic and, optionally, actions performed
in a datapath.
 Flowchart vs. ASM
Conventional flowchart
(i) Sequential way of representing procedural steps and decision paths for
algorithm
(ii)No time relations incorporated
ASM chart:
(i)Representation of sequence of events together with timing relations
between states of sequential controller and events occurring while moving
between steps.
A system clock, A serial bit clock, and Traffic Light Controller
The structure of a state
machine
A diagram of a memory write
machine.
 ASM Chart Elements
• States box :The State Box is a rectangle,
marked with the symbolic state name
• Outputs box: The Conditional Output Box is
an oval with entry from a decision block and
outputs activated for the decision conditions
being satisfied.
• Branches
• Conditional box
 States
•Each active transition of the clock causes a
change of state from the present state to the
next state.
•The ASM chart describes the control
algorithm in such a way that, given the present
state, the next state is determined
unambiguously for any values of the input
variables.
 A purely sequential
ASM.

A sequence is an
inherent property
of an ASM chart;
state Y follows
state X, and so on
 Outputs.
• The function of a controller is to send properly
sequenced outputs (voltage command signals)
to the controlled device according to some
algorithm.

ASM output notations

 Branches
• The next state is determined not only by the
present state but also by the present value of
one or more test (status) inputs
An ASM with a conditional
branch
Alternative representations of a three-way
branch
Conditional outputs
A simple ASM with a
state assignment
Binary Multiplier
 Multiplication is initiated by
the first clock pulse that
occurs after the “Go” input
is set HI.
 IDLE= 1, the circuit is not
busy, i.e. ready to multiply
 multiply operation is taking
place, IDLE = 0.
 IDLE and Go may be used
to coordinate the timing of
the binary multiplier with
the external user.
 Multiplier Example: Block Diagram
n21 IN
n
Multiplicand

Counter P Register B

log2 n n

Zero detect
G (Go) C
out Parallel adder

Z n n
Control Qo Multiplier
unit
0 C Shift register A Shift register Q

4
1. Load n
2. Shift Product
Control signals
3. Add OUT
4. Clock
Multiplier Example: ASM Chart
IDLE

MUL0

0 1
G
0 1
Q0
C ← 0, A ← 0
P←n– 1
A ← A + B,
C ← Cout

MUL1
C ← 0, C || A || Q ← sr C || A || Q,
P← P–1

0 1
Z
 Multiplier Example: Operation

1. The multiplicand (top operand) is loaded into register B.

2. The multiplier (bottom operand) is loaded into register Q.
3. Register C|| Q is initialized to 0 when G becomes 1.
4. The partial products are formed in register C||A||Q.
5. Each multiplier bit, beginning with the LSB, is processed (if bit is 1, use
adder to add B to partial product; if bit is 0, do nothing)
6. C||A||Q is shifted right using the shift register
– Partial product bits fill vacant locations in Q as multiplier is shifted out
– If overflow during addition, the outgoing carry is recovered from C during
the right shift
7. Steps 5 and 6 are repeated until Counter P = 0 as detected by Zero detect.
– Counter P is initialized in step 4 to n – 1, n = number of bits in multiplier
 Multiplier Example: Control Signal Table
Control Signals for Binary Multiplier

Bloc k Dia g ram Contr ol Contr ol

Module Microope ration Si gn al N ame Exp ression

Register A : A←0 Initialize IDLE · G

A← A + B Load MUL0 · Q
C ||A ||Q ← sr C ||A ||Q Shift_dec M UL1
Register B : B ← IN Load_B LO ADB
F lip-F lop C : C← 0 Clear_C IDLE · G + MUL1
C ← C out Load —
Register Q : Q ← IN Load_Q LO ADQ
C ||A ||Q ← sr C ||A ||Q Shift_dec —
Cou nter P : P← n–1 Initialize —
P ← P –1 Shift_dec —
 Multiplier Example: Control Table (continued)

• Signals are defined on a register basis

• LOADQ and LOADB are external signals controlled from the
system using the multiplier and will not be considered a part
of this design
• Note that many of the control signals are “reused” for different
registers.
• These control signals are the “outputs” of the control unit
• With the outputs represented by the table, they can be removed
from the ASM giving an ASM that represents only the
sequencing (next state) behavior
Multiplier Example - Sequencing Part of ASM

IDLE 00

0 1
G

MUL0 01

MUL1 10

0 1
Z
 Speeding Up the Multiplier
• In processing each bit of the multiplier, the
circuit visits states MUL0 and MUL1 in
sequence.
• By redesigning the multiplier, is it possible to
visit only a single state per bit processed?
 Speeding Up Multiply (continued)
• Examining the operations in MUL0 and MUL1:
– In MUL0, a conditional add of B is performed, and
– In MUL1, a right shift of C || A || Q in a shift register, the
decrementing of P, and a test for P = 0 (on the old value of P) are all
performed in MUL1
• Any solution that uses one state must combine all of the
operations listed into one state
• The operations involving P are already done in a single state,
so are not a problem.
• The right shift, however, depends on the result of the
conditional addition. So these two operations must be
combined!
 Speeding Up Multiply (continued)
• By replacing the shift
IDLE
register with a
combinational shifter
and combining the
adder and shifter, 0
G
1
the states can be merged.
A 0
• The C-bit is no longer needed. P n –1
• In this case, Z and Q0
MUL
have been made into P P–1
a vector. This is not A || Q sr C out || (A +0) || Q A || Q sr Cout || (A +0) || Q
essential to the
00
solution. 10
01 Z || Q0 11
• The ASM chart =>

A || Q sr Cout || (A +B) || Q A || Q sr Cout || (A+B) || Q

 Summary of Design Guidelines
.

• Basic Approach to Solving a Digital Problem

(a) Design from the top down.
(b) Separate the architecture from the control.
(c) Refine the design, letting the control algorithm and the
architecture influence each other as you converge on the solution.
Technical Design Considerations
(a) Use synchronous (clocked) design techniques.
(b) Avoid asynchronous inputs in the algorithm.
(c) Make your designs static-independent of clock speed.
A Courteous Philosophy
(a) Develop good documentation during the design.
(b) Keep designs modular and simple.
(c) Avoid obscure tricks.