8085

Microprocessor
Architecture

Dayanand K
 8085

UNIT 1 BASIC CONCEPTS 9 Hrs.

8085 Microprocessor - Architecture and its operation, Concept of instruction
execution and timing diagrams, fundamentals of memory interface -
Addressing modes
 8085

8085
The features of INTEL 8085 are :
• It is an 8 bit processor. (ALU-8-BIT)
• It is a Dual In-line Package (DIP) with 40 pins.
• It has Lower Order-multiplexed 16-Bit Unidirectional
ADDRESS BUS (A0-A15) and 8-Bit Bidirectional DATA
BUS (AD0-AD7).
• It works on 5 Volt dc power supply.
• The maximum clock frequency is 3 MHz while minimum
frequency is 500kHz.
• It provides 74 instructions with 5 different addressing modes.
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8085
• It provides 16 address lines so it can access 2^16 =64KBytes of
memory.
• It generates 8 bit I/O address so it can access 2^8=256
input/output ports.
• It provides 5 hardware interrupts: TRAP, RST5.5, RST6.5,
RST7.5, INTR. And an INTA (interrupt Acknowledge)
• It provides ACC (Accumulator) , One FLAG register (F) ,6
General Purpose registers (B, C, D, E, H, L) and two special
purpose registers(SP,PC).
• It provides serial lines SID ,SOD. So serial peripherals can be
interfaced with 8085 directly.
 8085

8085 PIN DIAGRAM

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8085 PIN DESCRIPTION

•  
 8085

8085 PIN DESCRIPTION

 READY: This an output signal used to check the status of
output device. If it is low, µP will WAIT until it is high.
 TRAP: It is an Edge triggered highest priority , non mask
able interrupt. After TRAP, restart occurs and execution
starts from address 0024H.
 RST5.5,6.5,7.5:These are maskable interrupts and have
low priority than TRAP.
 INTR¯&INTA:INTR is a interrupt request signal after which
µP generates INTA or interrupt acknowledge signal.
 IO/M¯:This is output pin or signal used to indicate
whether 8085 is working in I/O mode(IO/M¯=1) or
Memory mode(IO/M¯=0 ).
 8085

8085 PIN DESCRIPTION

 HOLD & HLDA:HOLD is an input signal .When µP receives
HOLD signal it completes current machine cycle and stops
executing next instruction.In response to HOLD µP generates
HLDA that is HOLD Acknowledge signal.
 RESET IN: This is input signal. When RESET IN is low µp
restarts and starts executing from location 0000H.
 SID: Serial input data is input pin used to accept serial 1 bit
data .
 X1X2 :These are clock input signals and are connected to
external LC, or RC circuit. These are divide by two so if 6 MHz
is connected to X1X2, the operating frequency becomes 3
MHz.
 VCC & VSS: Power supply VCC=+ -5Volt& VSS=-GND
reference.
 8085

8085 ARCHITECTURE
 8085

8085 ARCHITECTURE
Arithmetic & Timing & Control Register Unit
Logic Unit (ALU) Unit

Instruction Interrupt Control Serial

Decoding Unit Unit Communication
Unit

Bus Control Unit

 8085

Power Supply
2 Pins –
Vcc -(+5 V),
Vss - Ground
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Timing & Control Unit

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Timing & Control Unit

14 Pins-
Clock Generation -3 Pins
Ready – 1 Pin
Control – 3 Pins
Status – 3 Pins
DMA- 2 Pins
Reset – 2 pins

Till Now 16 Pins

 8085

Timing & Control Unit

6 MHz Crystal Oscillator

To other Ics for Synchronisation

Clock Generation -3 Pins

***6 MHz Crystal Oscillator connected to pins X1 & X2. Then the frequency is divided by 2.
thus final frequency used by the clock generator in 3 MHz.
** CLOCKOUT signal is given to other Ics connected to the Processor for synchronisation
 8085

Timing & Control Unit

Ready – 1 Pin
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Timing & Control Unit

Control & Status Pins – 3 + 3 = 6 Pins

IO- INPUT OUTPUT

M- MEMORY

WHEN IO/M IS ‘1’, THEN IO DEVICES ARE INTERFACED

WITH PROCESSOR.
WHEN IO/M IS ‘0’, THEN MEMORY DEVICES ARE
INTERFACED WITH PROCESSOR.
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Timing & Control Unit

IO/M’ RD’ WR’ OPERATION
0 0 1 MEMRD’ MEMORY READ
0 1 0 MEMWR’ MEMORY WRITE
1 0 1 IORD’ INPUT OUTPUT READ
1 1 0 IOWR’ INPUT OUTPUT WRITE

EXAMPLE: WHEN RAM OR ROM IS TO BE READ THE

SIGNAL IS
MEMRD’
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Timing & Control Unit

ALE MEMORY READ
1
0
A8-A15 (HIGHER ADDRESS BUS)
MEMORY
HIGHER 8- LOWER 8-
BIT ADDR BIT ADDR 8 BIT DATA
AD0-AD7 (LOWER ADDRESS AND DATA
BUS)
16 BIT ADDRESS

8085 IO/M’
0
1
INPUT OUTPUT
RD’ 0
1 DEVICES

WR’ 0
1

0 S1
1 S0 0
1
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Timing & Control Unit

ALE MEMORY WRITE
1
0
A8-A15 (HIGHER ADDRESS BUS)
MEMORY
HIGHER 8- LOWER 8-
BIT ADDR BIT ADDR
8 BIT DATA
AD0-AD7 (LOWER ADDRESS AND DATA
BUS)
16 BIT ADDRESS

8085 IO/M’
0
1
INPUT OUTPUT
RD’ 0
1 DEVICES

WR’ 0
1

0 S1
1 S0 0
1
 8085

Timing & Control Unit

ALE IO READ
1
0
A8-A15 (HIGHER ADDRESS BUS)
MEMORY
LOWER 8-
BIT ADDR
AD0-AD7 (LOWER ADDRESS AND DATA
BUS)
8 BIT ADDRESS

8085 IO/M’
0
1
INPUT OUTPUT
8 BIT DATA
RD’ 0
1 DEVICES

WR’ 0
1

0 S1
1 S0 0
1
 8085

Timing & Control Unit

ALE IO WRITE
1
0
A8-A15 (HIGHER ADDRESS BUS)
MEMORY
LOWER 8-
BIT ADDR
AD0-AD7 (LOWER ADDRESS AND DATA
8 BIT DATA BUS)
8 BIT ADDRESS

8085 IO/M’
0
1
INPUT OUTPUT
RD’ 0
1 DEVICES

WR’ 0
1

0 S1
1 S0 0
1
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Arithmetic & Logic Unit

 8085

Register Unit
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Instruction Decoding Unit

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Interrupt Control Unit

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Interrupt Control Unit

Interrupts
Hardware or Pin Interrupts
5 Interrupts
Priority
Highest – TRAP
RST7.5
RST6.5
RST5.5
Lowest – INTR

Acknowledge for INTR is INTA

 8085

Serial communication Unit

 8085

Bus Control Unit

 8085

FLAG REGISTER
Flag Register is given by:

S Z X AC X P X CY
S: Sign flag is set when result of an operation is negative.
Z:Zero flag is set when result of an operation is 0.
AC:AUXILIARY carry flag is set when there is a carry out of lower
nibble or lower four bits of the operation.
CY:Carry flag is set when there is carry generated by an
operation.
P:Parity flag is set when result contains even number of 1’s.
Rest are don’t care flip flops.
 8085

FLAG REGISTER
Flag Register is given by:
S Z X AC X P X CY
S: Sign flag is set when result of an operation is negative.
After any ALU operation, MSB of the Operated Register is
copied into the Sign Flag.
For Example if C register content is incremented,
1 0 0 1 1 1 0 1
 Then SIGN flag is SET to ‘1’
For Example if A&B register content is Added and result in A is

0 0 0 1 1 1 0 1
 Then SIGN flag is RESET to ‘0’
 8085

FLAG REGISTER
Flag Register is given by:
S Z X AC X P X CY
S: Sign flag is set when result of an operation is negative.
After any ALU operation, MSB of the Operated Register is
copied into the Sign Flag.
For Example if C register content is incremented,
1 0 0 1 1 1 0 1
 Then SIGN flag is SET to ‘1’
For Example if A&B register content is Added and result in A is

0 0 0 1 1 1 0 1
 Then SIGN flag is RESET to ‘0’
 8085

FLAG REGISTER
Flag Register is given by:
S Z X AC X P X CY
Z: Zero flag is set when result of an operation is 0.
After any ALU operation, if the result is ’00’, then Zero flag is
SET.
For Example if C register content is decremented,
0 0 0 0 0 0 0 0
 Then ZERO flag is SET to ‘1’
For Example if A&B register content is Added and result in A is

0 0 0 1 1 1 0 1
 Then ZERO flag is RESET to ‘0’
 8085

FLAG REGISTER
Flag Register is given by:
S Z X AC X P X CY

CY: Carry flag is set when there is carry generated by an operation.

After any ALU operation, The Carry flag is SET when,

Condition 1: The result of 8-bit Operation generates 9th BIT,

Condition 2: the result of 16 –bit Operation generates 17th BIT

And also Carry flag is affected when

Condition 3: in Rotation of bits, if carry is included

Condition 4: if Borrow is generated in case of Subtraction in both 8-bit and

16-bit operations
 8085

FLAG REGISTER
Flag Register is given by:
S Z X AC X P X CY
 8085

FLAG REGISTER
S Z X AC X P X CY
AC: AUXILIARY carry flag is set when there is a carry out of lower
nibble or lower four bits of the operation.
 8085

FLAG REGISTER
S Z X AC X P X CY
P: Parity flag is set when result contains even number of 1’s.
Rest are don’t care flip flops.
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FLAG REGISTER
S Z X AC X P X CY
0 0 0 0 0 1 0 1
F=05