Reference Methodology

Tessent MemoryBIST Flow

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Introduction

What is BIST?

 Built-in Self Test, or BIST, is a technique of designing

additional hardware and software features into integrated
circuits to allow them to perform self-testing, i.e.: testing
of their own operation (functionally, parametrically, or
both) using their own circuits, thereby reducing the
dependence on an external automated test equipment
(ATE).

 Hence, Memory BIST (commonly referred to as MBIST) is

the technique of testing memories embedded in integrated
circuits by applying, reading and comparing test patterns
designed to expose defects in the memory device.

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Introduction (continued)

Below is a generic block diagram of a MemoryBIST

architecture:

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Introduction (Tessent)

What is Tessent?
Tessent is a suite of software automation tools that generates and
inserts the Embedded Test Controllers (i.e. BIST) into Integrated
Circuits that allow self-testing and failure diagnostics of embedded
memories.

Features, such as top-down or bottom-up flow, greatly improves the

embedded test insertion predictability. Tessent supports WTAP, a
distributed version of the central TAP using the IEEE 1500 protocol,
which allows complete physical block footprint predictability.

Various embedded test objects that can be inserted into your design
using the Tessent Hierarchical Integrated Flow tools include the
following:
• Memory BIST controllers
• LogicTest controllers (LBIST)
• Boundary scan registers
• IEEE 1149.1 Circuit test access port (TAP)
• IEEE 1500 Core wrapper test access ports (WTAP)

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Introduction (Tessent)

Below is a block diagram at the Chip-Level with Embedded Test from

Tessent. It shows the top-level TAP driving the block-level distributed
Wrapper TAP (WTAP). The WTAP in-turn drive the embedded MBIST
and LBIST controllers.

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How to insert MBIST into Integrated Circuits

There are two techniques (methods) of inserting MBIST into

an integrated circuit:
 RTL

 GATE

This presentation focuses on the RTL MBIST insertion flow at

the block-level, using the Mentor Graphics Tessent
MemoryBIST tool.

DISCLAIMER: please refer to the Mentor Graphics Tessent MemoryBIST

Usage Guide and Reference documents for additional information and in-depth
details.

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RTL Design Flow (overview)

7
GATE-Level Design Flow (overview)

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Getting Started: Tessent MemoryBIST flow (overview)

Whether for RTL or GATE-Level netlist, the Mentor Graphics

Tessent MemoryBIST flow is comprised of 5 steps, which are
performed at different stages within the flow:

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Getting Started: Tessent MemoryBIST flow (contd)

 Step 1: ETChecker – checks if a design meets the embedded test

requirements, identifies where test-point locations and dedicated
isolation will be inserted and extracts all pertinent design
information from the RTL or netlist.
 Step 2: ETPlanner – Plans your embedded test insertion and
generates the needed Tessent Integrated Flow environment.

 Step 3: ETAssemble – Inserts the embedded test controllers,

such as WTAP, memory BIST Controller and Interface Collars.

 Step 4: Prelayout ETSignOff – Performs pre-layout ETSignOff

using rule checkers, Static timing analysis, formal verification, and
simulations.
 Step 5: Final ETSignOff – Performs final post-layout ETSignOff
using rule checkers, Static timing analysis, formal verification, and
simulations.

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Preparation: What do you need to begin?

You will need to prepare the following items before you

begin:
 Memory Library Models:
 Verilog Simulation Model (*.v)
 LogicVision Scan Model (*.memlib or *.lvlib)

 Standard Cell Library Models:

 Verilog Simulation Model (*.v)
 LogicVision Scan Model (*.scan)
 Synopsys Liberty Model (*.lib)

The Verilog simulation and Synopsys Liberty models are

provided by the foundry.

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Preparation: Generating the LogicVision Scan Models

You can generate the LogicVision Scan Models for the

Standard cells using the Tessent ETLibGen tool:

etlibgen gf28 \
-mode nonScan \
-libertyFile <technology>.lib \
-y ./verilog \
-scanmodelExtension scan \
-configFile gf28.etlib

Once you have prepared your work area; and setup the
library models you need, we can now begin the individual
steps for the RTL flow.

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Step One: ETChecker

Step One: ETChecker is comprised of the following four (4)

sub-steps, represented in the block diagram below:

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Step One: ETChecker

1.etchecker <design> -gentemplate ON

 Generates the template file: <design>.etchecker
 Generates a Makefile
 Modify the template file sections: “lv.target”, “lv.EmbeddedTest”, “lv.Assert”
 Modify the Makefile section: “etcOptions”, “BATCH=on|off”

2.make <design>.clockInfo
 Extracts clock information from the design
 Review the following log and report files:
 etCheckInfo/etchecker.log_clockInfo
 etCheckInfo/etchecker.rpt_clockInfo
 Review the following design output files:
 etCheckInfo/etp/<design>.etpClockTree
 etCheckInfo/etp/<design>.etpClockDomainInfo
 etCheckInfo/etp/<design>.etpConstraints

 Update the template file generated in (#1): <design>.etchecker with

the clock information extracted
 Modify the template file section: “lv.ClockDomainBase”
 Modify the template file section: “lv.InternalClocksource”

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Step One: ETChecker (success)

3.make <design>.ruleCheck
 Performs design rule checks (DRC) on the design
 Review the following log and report files:
 etCheckInfo/etchecker.log_ruleCheck
 etCheckInfo/etchecker.rpt_ruleCheck

Success is achieved ONLY by the creation of the following

directory and output file(s):
4. etcHandoff/<design>.etCheckerInfo
 No error message reported
 No fatal severity message reported

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Step Two: ETPlanner

Now that the “checking” portion of the design is complete, we

begin the planning section of the flow. This is the stage
where test trade-offs are made based on:
 Test quality
 Test time
 Power consumption
 Area

However, before we begin; to maintain consistency between

design groups, it is useful to create Global Definition files that
can be used by everyone involved in the same project.

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Step Two: ETPlanner (Global Definition Files)

What is a Global Definition file?

 Global Definition files: contain information used at
different stages of the flow to maintain consistency
among different design groups involved in the same
project.
 Maintenance and support of the Global Definition files
by a single DFT entity is possible, and no designers will
be left behind for environment details
 The 3 Global Definition files recommended are:
 ICTechnology file
 CADEnvironment file
 ETDefaults file

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Step Two: ETPlanner (Global Definition Files - contd)

1. ICTechnology file:
 Specifies the directory path location of all required technology libraries,
such as: Verilog simulation models, LogicVision scan models, Synthesis
models, etc.

2. CADEnvironment file:
 Specifies the default simulator (example: Cadence NCVerilog, Synopsys
VCS, Mentor Graphics ModelSim), and the simulation commands you want
to use (example: ncxlmode, vcs, vlog).
 Specifies the synthesis tool to be used (example: Synopsys DC-Compiler)
 Specifies the command to create directories (example: /bin/mkdir)
 Specifies the command to create soft links (example: /bin/ln –s)

3. ETDefaults file:
 Defines all embedded test defaults for Memory BIST and Logic BIST; such
as diagnostic features, power limits, algorithm selection, etc.

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Step Two: ETPlanner

Step Two: ETPlanner is comprised of the following three (3)

sub-steps, carried out in this order:
1.Generate the Embedded test plan template files: <design>.etplan; and
<design>.etplan.README
etplanner <design> \
-mode genPlan \
-etCheckerInfoFile ../etchecker/etcHandoff/<design>.etCheckerInfo \
-CADEnvFile ./CentralFiles/HWLib.CADEnv \
-ICTechFile ./CentralFiles/gf28.LVICTech \
-etDefFile ./CentralFiles/HWLib.ETDefaults \
-etplanFile <design>.etplan \
-memLib ../LIBS/srams/*.memlib \
-outDir outDir \
-log ./logfiles/etplanner.log_genPlan

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Step Two: ETPlanner (contd)

Review and update the following sections in the <design>.etplan

file, refer to the <design>.etplan.README file for additional
instructions:
 CADEnvironment: ./CentralFiles/*.CADEnv
 ICTechnology: ./CentralFiles/*.LVICTech
 DesignSpecification
 RTL | Gate Extension
 Modules RTL | Gate

 Embedded Test
 Global Options
 Module Options
 MemBistControllerOptions
 MemBistStepOptions
 MemBistCollarOptions

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Step Two: ETPlanner (contd)

Once we are satisfied with our chosen options, the following

steps confirms the plan, and generates all the necessary files,
soft links, and workspaces:
2.make checkPlan
 Verifies the Embedded Test Plan and generates a report
 Review the output file: OutDir/<design>.ETSummary to make sure your
specifications are met (example: Test time, Power)
 If your specifications are not met, return back to ETChecker (Step One), or
modify <design>.etplan from (#1.) and re-run (#2.) -> make checkPlan

3.make genLVWS
 Verifies the Embedded Test Plan
 Generates the LVWorkSpaces for the implementation of the plan

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Step Two: ETPlanner (flow)

To summarize, below is a block diagram representing

the steps in the ETPlanner flow:

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Step Two: ETPlanner (success)

Success is achieved ONLY by the creation of the

following directory and output file(s):
 OutDir/<design>.membist_checkPlan
 Describes the memory BIST architecture that will be implemented

 Review the following log files to make sure no errors or fatal

severity messages are reported:
 OutDir/etplanner.log_checkPlan
 OutDir/etplanner.log_genLVWS

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Review of Rule Checking and Planning

At this point of the flow, let’s review the steps we have just
completed:
a) Step One: ETChecker
 Checked the design for Embedded Test compliance
 Executed in two (2) modes: “clockInfo” and “ruleCheck”
 Success was demonstrated by the generation of the file
<design>.etCheckerInfo in the etcHandoff directory

b) Step Two: ETPlanner

 Plan the Embedded Test solution
 Success was demonstrated by the generation of the file
<design>.ETSummary, and the file
outDir/<design>.membist_checkPlan
 Success was also demonstrated by the generation of the LV workspace
directories, where the plan will be implemented

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Step Three: ETAssemble

Now that the “checking” and “plan” portion of the design is

complete, we begin the “assemble” section of the flow. This
is the stage where the actual implementation of the
Embedded Test Plan is executed.
 There are seven sub-steps required to be executed in Step
Three. These sub-steps are well documented in the
generated Makefile and README files located in the LV
workspace directory. Review these files for additional
information.
 You will need to change directory to the
<design>_LVWS/ETAssemble to start the
implementation.

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Step Three: ETAssemble

1. make embedded_test:
 Generate and insert the WTAP, memory BIST controllers into your design
 The generated BIST files are written into the ./outDir directory, verify that
they exist (i.e.: *.v), and also the timing constraint files (i.e. *.sdc)
 Review log file: ./outDir/etassemble.log to make sure no error
messages are reported, and warning messages are understood.

2. make mbist_full_sim:
 Run a full address simulation using the memory assembly module to verify
the memory BIST controllers are operating correctly
 Review the log file:
./outDir_etv/verilog.log_membistv_P1_<design>_int_MBIST_asse
mbly_rtl

3. make designe:
 Generate the <design>.tcm file, and extract connection information
 Review the log file: outDir/designe.log_<design>

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Step Three: ETAssemble

4. make config_etSignoff:
 Generate the <design>.signoff testbench configuration file, which is
required to perform early verification of all Embedded Test features.
 Review the log file: ./outDir_etv/etv.log_config_etSignOff

5. make lvdb_prelayout:
 Generate the pre-layout circuit database
 Review the log file: ./outDir_etv/etv.log_CreateLVDB

6. make testbench:
 Generate the testbench based on (#4.) above for early verification
 Review the log file: ./outDir_etv/etv.log_testbench

7. make sim:
 Simulate the testbench created in (#6.) on the entire RTL design with the
embedded test controllers
 Review the log files: ./outDir_etv/verilog.log_wtapbist_DP1 and
./outDir_etv/verilog.log_membistv_P1_<design>

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Step Three: ETAssemble (success)

Success is achieved when:

1. All generated log files reviewed report no error messages, and
warning messages are understood.
2. Simulation performed in (#.7) is error free, meaning no mis-
compares are reported at the end of simulation for both the WTAP
and MEMBIST steps:

513000 * Resetting the WTAP with the signal WRSTN

518000 * Shifting Instruction register and expecting inverted default
518000 Instruction after a reset 111...
[statusEnable=1]...1[01] being shifted out.
550000
550000 End of the WTAP TESTLOGICRESET Test
Simulation finished at time = 550000
Number of Z Compare Events = 0
Number of 1/0 Compare Events = 309
Number of Compare Failures = 0

Simulation complete via $finish(1) at time 55 US + 0

./outDir_etv/wtapbistv_DP1.v:106 $finish;

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Step Three: ETAssemble (success contd)

56896 Starting controller abric_CLK625MHz_int_MBIST1_cntrl

----- 0% -----
----- 10% -----
----- 20% -----
----- 30% -----
----- 40% -----
----- 50% -----
----- 60% -----
----- 70% -----
----- 80% -----
----- 90% -----
----- 100% -----
66272 Checking that signal DONE is YES on IR_STATUS0
66400 Checking that signal GO is PASS on IR_STATUS1
69808
Simulation finished at time = 69808
Number of Z Compare Events = 0
Number of 1/0 Compare Events = 21
Number of Compare Failures = 0
Simulation complete via $finish(1) at time 6980800 PS + 0
./outDir_etv/membistv_P1_abric.v:116 $finish;

3. Verify and review the generated Timing constraints for the MBIST
controller: ./outDir/<design>_etassemble.sdc

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Step Four: Pre-Layout ETSignOff

1. Synthesis:
 Generate GATE-level synthesized netlist by synthesizing the RTL
 Original RTL files (*.v), plus the Tessent modified RTL files (*.v_et)
 Generated MemBIST controller RTL files (*.v)
 Generated WTAP RTL files (*.v)
 Consolidate the timing constraints for synthesis:
 Functional SDC
 MemBIST Controller SDC [from (#1.) in the Step Three]

2. Formal Verification:
 Execute formal verification on the RTL-to-RTL netlist
 GOLDEN: Original RTL files (*.v)
 REVISED: The Tessent modified RTL files (*.v_et)
 Execute formal verification on the RTL-to-GATE netlist
 GOLDEN: Original RTL (*.v), plus Tessent modified RTL (*.v_et) files
 REVISED: pre-layout synthesized GATE-Level netlist

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Step Four: Pre-Layout ETSignOff (success)

3. Simulation:
 Perform simulation on the pre-layout synthesized GATE netlist [from
(#1.) in step four] to ensure the testbench validates the WTAP and MBIST
operation of the BIST Controller, Collars and Memories.

4. Hand-Off to Layout:
 Prepare the database to hand-off to Layout

Success is achieved when:

1. Formal Verification: reports no errors among the following databases
 RTL-to-RTL: verification is error free
 RTL-to-GATE: verification is error free

2. Simulation performed on the synthesized GATE-Level netlist [from step

(#.3) above] is error free, meaning no mis-compares are reported
at the end of simulation for both the WTAP and MEMBIST steps (see
simulation snapshot for example).

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Step Five: Post-Layout ETSignOff

1. Formal Verification:
 Execute formal verification on the RTL-to-GATE netlist
 GOLDEN: Original RTL (*.v), plus Tessent modified RTL (*.v_et) files
 REVISED: post-layout Synthesized GATE-Level netlist
 Execute formal verification on the GATE-to-GATE netlist
 GOLDEN: pre-layout synthesized GATE-Level netlist
 REVISED: post-layout synthesized GATE-Level netlist

2. Simulation:
 Perform parasitic back-annotated simulation on the post-layout GATE
netlist to ensure the testbench validates the MBIST operation of the BIST
Controller, Collars and Memories.

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Step Five: Post-Layout ETSignOff (success)

Success is achieved when:

1. Formal Verification: reports no errors among the following databases
 RTL-to-GATE: verification is error free
 GATE-to-GATE: pre-layout versus post-layout verification is error free

2. Parasitic back-annotated simulation performed on the post-layout

GATE-Level netlist [(#.2) from step five] is error free, meaning no
mis-compares are reported at the end of simulation for both the
WTAP and MEMBIST steps (see simulation snapshot for example).

3. Hand-Off to Chip-Level Integration:

 Prepare the database to hand-off for Chip-Level Integration

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Reference Methodology Database Location

A Reference Methodology for the Tessent MemoryBIST RTL

flow exists in the following directory location:
 Directory location:
 /remote/proj4/infotech/poc/poc12_sjc

 RTL Source Code:fromCustomer

 DFT: MBIST/RTL
 Formal Verification: LEC
 Synthesis: SYNTH
 ATPG: ATPG
 Simulation: SIM
 Static Timing Analysis: STA
 Memory Library Models: LIB/srams
 Standard Cell Models: LIB/std/cmos
 Tutorial location:
 /
remote/tools/linux/mentor/tessent_2009_5/tessent_SoC_2009_5
.EP03/ETCreate/support/ETCreate/training
 -rw-r--r-- 1 cadmgr lmadmin 374049 Mar 31 2010 LV2005_ELT_Hier_Day2.pdf
 -rw-r--r-- 1 cadmgr lmadmin 15313143 Mar 31 2010 LV2005_ELT_Hier_Day2.tgz
 -rw-r--r-- 1 cadmgr lmadmin 292941 Mar 31 2010 LV2005_EMT_Flat_Day1.pdf
 -rw-r--r-- 1 cadmgr lmadmin 2821000 Mar 31 2010 LV2005_EMT_Flat_Day1.tgz

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Acknowledgements

THANK YOU

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