MICRO133: Microprocessor Systems

Prelim Lecture 4 & 5

INTEL P ADDRESSING
MODES, AND
INSTRUCTION ENCODING
AND DECODING
Lecture’s Objectives
Intel P Addressing Modes, and Instruction Encoding and
Decoding

 After this lecture, student should be able:

To describe the different the operations of
microprocessor’s addressing modes,
To select the appropriate addressing mode to
accomplish a given task,
To describe the sequence of events that place data
onto the stack or remove data from the stack,
To explain the operation of each data movement
instruction with applicable addressing modes,
To determine the symbolic opcode, source,
destination, and addressing mode for a hexadecimal
PART 1

Microprocessor’s
Addressing Modes
Introduction
Microprocessor’s Addressing Modes

Addressing Modes
 refer to a set, of the number of ways, in which the data used by a
program can be accessed by a CPU.

The number of ways of accessing data depends on the type

of data and the logical location of the data.

In high-level languages (HLL) the name of a variable is

sufficient information needed to access the data, assigned to
the variable’s name.

Using DEBUG the assembly language programmer needs to

choose the most appropriate addressing mode, in order to
access data at a known address.
Introduction
Microprocessor’s Addressing Modes

Accessing data in high-level language such C, C++, or Pascal

 C = A + B

Accessing data in DEBUG or Assembly

 MOV AX,[0200] ;the A value

 MOV BX, [0202] ;the B value
 ADD AX, BX ;A + B
 MOV [0300], AX ;store result at C

Choice of addressing mode used depends upon the type of data being
accessed.

 A constant,
 A variable piece of information or
 An item within an array of data.
8088/8086 Instruction
Syntax
Microprocessor’s Addressing Modes

Intel family supports four (4) addressing modes (in general)

Modes differ in the location data and address calculations

All modes involves physical address generation

8086 Instruction Syntax

 
Lines of code

 Label: Instruction ;comment/s

Instruction
 Opcode [operand 1], [operand 2]
 Mnemonic Destination Source
8088/8086 Instruction
Syntax
Microprocessor’s Addressing Modes

Operands
These are destination address and source address of data.

Opcode (OPeration CODE)

This tells the microprocessor which operation to perform

The way in which these addresses are specified is

named the addressing mode for the source and
destination address.

Source operand is to the right

Destination operand is to the left
Types of Addressing Modes
Microprocessor’s Addressing Modes

Data Addressing Modes

 Register Addressing Mode (General)
 Immediate Addressing Mode (Constant)

Memory Addressing Modes

 Direct Addressing Mode (Variable)
 Register Indirect Addressing Mode (Arrays)
 Base-plus-Index Addressing Mode (Complex Array)
 Register Relative Addressing Mode (Complex Array)
 Base-Relative-plus-Index Addressing Mode (More Complex Array)
 Scaled-index Addressing Mode (More Complex Array for 32 bit)
 RIP Relative (for 64-bit processors)

Program Memory Addressing Modes

 Direct Program Memory Addressing Mode
 Register Indirect Program Memory Addressing Mode
 Memory Indirect Program Memory Addressing Mode
 Relative Program Memory Addressing Mode (Conditional)

Stack Memory Addressing Modes

Data Addressing Modes
Microprocessor’s Addressing Modes

Register Addressing Mode (General)

It uses the name of a register to identify the location of data – the
data is held in the register.
Copy the content source register to a destination register
8 Working Registers – AX, BX, CX, DX, SI, DI, BP, SP – 16 bit wide.
Four of the registers – AX, BX, CX, DX can be thought of as single
16 bit registers or dual 8 bit registers.
Length of the registers must match

MOV AX, CX Legal instruction

MOV BL, CL Legal instruction
MOV AL, SI Illegal instruction
MOV AX, CH
Illegal instruction
MOV DS, AX
Legal instruction
MOV CS, AX
Illegal instruction
Data Addressing Modes
Microprocessor’s Addressing Modes

Table 1. Other examples of register-addressed instructions.

Data Addressing Modes
Microprocessor’s Addressing Modes

Immediate Addressing Mode (Constant)

 Transfer data (constant) to into a destination register

 Value moved into a register (from instruction)
 Most instructions assume that the operands of an instruction are the address of the data
involved, not the data itself.
 The exception to this rule is the immediate addressing mode, where the actual data number
is specified in the instruction and is hard coded as part of the instruction (source operand).

ITEM1 EQU0F3h
ITEM2 EQU01110101000010b
ITEM3 EQU0

START:MOVAX, ITEM1 Legal instruction

MOVBL, 87 Legal instruction
MOVCH, ITEM2 Illegal instruction
Illegal instruction
MOV 0CDH, BL
Illegal instruction
MOVITEM2, AL

 Note: EQU directive assigns names to constant numbers and does not save memory space
Data Addressing Modes
Microprocessor’s Addressing Modes

Table 2. Other examples of immediate addressing using the MOV instruction.

Some Symbols used in
Addressing Modes
Microprocessor’s Addressing Modes

Labels - These are names given to an address of an opcode in code memory

Constants - These are names assigned to absolutely constant numbers, hard

coded into instructions

Variables
 These are names of an address in memory
 However, a program reference to the variable name, as an operand, will use the contents of
address

LOOPHERE: MOV AX,BX

…
JMP LOOPHERE

CON1 EQU 0ABCDH

…
MOV AX,CON1

VAR1 DW 0ABCDH
…
MOV AX,VAR1
MOV VAR1,BX
Memory Addressing Modes
Microprocessor’s Addressing Modes

Accessing data that is in memory is done by specifying the

address of the data.
 Address is actually the offset of the data relative to the base of
the data segment.

This mode is invoked when the operand is placed in

square brackets [xxxx].

Direct Memory Addressing Mode (Variable)

 Move byte or word between memory location and a register

 Memory address appears in the instructions instead of data
 Data accessed from a location in memory
 [xxxx] is a fixed address number
Memory Addressing Modes
Microprocessor’s Addressing Modes

Examples of Direct Addressing Modes

MOV [1234H], AX ;MOVE CONTENT OF AX TO

;DS:1234H IS SUPPORTED!
VAR1 DW ?
VAR2 DB 0FFH
MOV VAR1,1234H ;MOVE NUMBER 1234H TO ;VARIABLE
VAR1
MOV [VAR1],AX
MOV VAR1+1,1234H
MOV WORD PTR [VAR1+1],1234H
MOV BYTE PTR [VAR1],12H
MOV VAR2,1234H
MOV AH,VAR2
Memory Addressing Modes
Microprocessor’s Addressing Modes

Table 3. Other examples of Direct memory addressed instructions using

EAX, AX, and AL and RAX in 64-bit mode.
Memory Addressing Modes
Microprocessor’s Addressing Modes

Register Indirect Addressing Mode (Arrays)

 
 Transfer data between a register and a memory
location address by a register
 Sometimes need using the special assembler
directives when size is not clear such as BYTE PTR,
WORD PTR, DWORD PTR.
VAR1 DD 12345678H
VAR2 DD 9ABCDEF0H
SUM DD ?
 
;MOVE LOW WORD OF VAR1 TO AX
START: MOV AX, WORD PTR [VAR1]
;MOVE LOW WORD OF VAR2 TO BX
MOV BX, WORD PTR [VAR2]
Memory Addressing Modes
Microprocessor’s Addressing Modes

MOV CX, WORD PTR [VAR1+2]

;MOVE LOW WORD OF VAR1 TO AX
MOV DX, WORD PTR [VAR2+2]
;ADD THE LOW WORDS
ADD AX, BX
;ADD THE HIGH WORDS
ADC CX, DX
;MOVE LOW WORD OF RESULT TO LOW WORD
;OF SUM
MOV WORD PTR [SUM], AX
;MOVE HIGH WORD OF RESULT TO HIGH
;WORD OF SUM
MOV WORD PTR [SUM+2], CX
RET
Memory Addressing Modes
Microprocessor’s Addressing Modes

Table 4. Other examples of register indirect memory addressing.

Memory Addressing Modes
Microprocessor’s Addressing Modes

 Base-plus-Index Addressing Mode

(Complex Array)

Transfer data between a register and a

memory location addressed by base register
and index register
 
MOV [BX+SI],AX
MOV DX,[BX+DI]
Memory Addressing Modes
Microprocessor’s Addressing Modes

Table 5. Other examples of base-plus-index memory addressing.

Memory Addressing Modes
Microprocessor’s Addressing Modes

 Register Relative Addressing Mode

(Complex Array)

Move data between a register and a

memory location addressed by specified
register plus displacement (offset)
 
MOV AX,[BX+4]
MOV BX,[SP+3]
Memory Addressing Modes
Microprocessor’s Addressing Modes

Table 6. Other examples of register relative memory addressing.

Memory Addressing Modes
Microprocessor’s Addressing Modes

 Base-Relative-plus-Index Addressing
Mode (More Complex Array)

Transfer data between a register and a memory

location addressed by base and index register
plus displacement
 
MOV [BX+SI+2],AX
MOV DX,[BX+DI+4]
Memory Addressing Modes
Microprocessor’s Addressing Modes

Table 7. Other examples of base relative-plus-index memory addressing.

Memory Addressing Modes
Microprocessor’s Addressing Modes

 Scaled-index Addressing Mode (More

Complex Array for 32 bit)
The address in the second register is modified by
scale factor
Scale factor are 1, 2, 4, or 8 for word, double
word, or quad-word access respectively.
Only available in 80386 and above
microprocessor (32 bit)

MOV [EBX+2*ECX], AX
MOV EAX, [EBP+8*ECX]
RIP Relative Addressing Modes
Microprocessor’s Addressing Modes

 An addressing mode is only available to the

64-bit extensions on the addressing Pentium
4 or higher.
 An addressing uses the 64-bit instruction
pointer register in the 64-bit mode to address
a linear location in the flat memory model
 A mode that allows access to any location in
the memory system by adding a 32-bit
displacement to the 64-bit contents of the 64-
bit instruction pointer
Data and Memory Addressing
Modes
Microprocessor’s Addressing Modes

Figure 1. 8086–Core2 data and memory-addressing modes

Program Memory Addressing
Modes
Microprocessor’s Addressing Modes

The flow of a program can be controlled through

the use of different branching instructions
Different addressing modes are also used here
to direct the CPU to various locations of program
code

Direct Program Memory Addressing Mode

 Jump to a location specified by a constant
 
JMP 0E001h ;JUMPS DIRECTLY TO
;CS:E001H
Program Memory Addressing
Modes
Microprocessor’s Addressing Modes

Register Indirect Program Memory Addressing Mode

Jump to a location specified by the contents of a register

JMP BX ;Jumps to the address contained in BX

Memory Indirect Program Memory Addressing Mode

Jump to a location given by the contents of two memory
locations pointed at by a register

JMP [DI] ;REPLACES IP WITH THE CONTENTS OF

THE ;MEMORY LOCATIONS POINTED
;AT BY DI AND DI + 1
Program Memory Addressing
Modes
Microprocessor’s Addressing Modes

Table 8. Other examples of indirect program memory addressing.

Program Memory Addressing
Modes
Microprocessor’s Addressing Modes

Relative Program Memory Addressing Mode

(Conditional)

Jump according to some condition to a memory

location that is within –128 or +127 bytes of the
current location

 JE(JZ) ;JUMP IF EQUAL/ZERO (Z = 1)

 JNE(JNZ) ;JUMP IF NOT EQUAL/ZERO (Z = 0)
 JB(JNAE) ;JUMP IF BELOW (C = 1)
 JAE(JNB) ;JUMP IF EQUAL OR ABOVE (C = 0)
 JS ;JUMP IF SIGN FLAG SET (S = 1)
 JNS ;JUMP IF SIGN FLAG NOT SET (S = 0)
 JCXZ ;JUMP IF CX IS ZERO (CX = 0)
Stack Memory Addressing
Modes
Microprocessor’s Addressing Modes

Stack is LIFO (Last In, First Out) in the memory

Data are place by PUSH and removed by POP
instruction

 Stack memory is maintained by stack segment (SS) and

stack pointer (SP) – SS:SP

 When a word is pushed, high 8-bits are stored at SP-1 and

low 8-bits are stored at SP-2, then SP is decremented by 2

 When a word is poped, low 8-bits are removed from the

location SP and high 8-bits are removed from the location
address by SP+1, at SP-2, then SP is incremented by 2
Stack Memory Addressing
Modes
Microprocessor’s Addressing Modes

Figure 1 – PUSH BX - place the contents of BX onto a stack

Stack Memory Addressing
Modes
Microprocessor’s Addressing Modes

Figure 2 – POP CX – removed data from the stack and place

them into CX
Stack Memory Addressing
Modes
Microprocessor’s Addressing Modes
Table 9. Examples of stack memory addressing using PUSH and POP
instructions
Calling Subroutines
Microprocessor’s Addressing Modes

Normally a complete program is written as a set of subroutines

To execute a subroutine a CALL instruction is used
CALL is similar to a procedure call in a high-level language

When executed it pushes IP and the return segment (for FAR calls) onto the stack, then
executes a jump to the call address

Two types of CALLs can be executed

CALL to a NEAR address – Only Offset (IP) specified, segment assumed to be the same
CALL to a FAR address – New Segment and Offset (IP) specified

CALL subroutine is terminated with a RET instruction

RET (RETurn) instruction causes the CPU to pop the RETURN address off the stack (IP or
Segment and IP) and execute a jump back to it

 CALL 0200
 CALL 1029:0200
NEAR vs. FAR Subroutine
Directives
Microprocessor’s Addressing Modes

 If the subroutine is situated in the same segment

as the routine that it has been called from, then
the subroutine is considered to be NEAR.

 If the subroutine is not situated in the same

segment as the routine that it has been called
from, then the subroutine is considered to be FAR.

 Jump to a location out of the current code segment,

meaning that not only IP but also CS is replaced with new
values

show sample program

PART 2

Microprocessor’s
Instruction Encoding
and Decoding
Overview
Intel µP Instruction Encoding and Decoding

 Machine Language (ML)

native binary code that the microprocessor understand.
 Assembler
use to translate assembly instruction to a machine code.
 Opcode (OPeration CODE)
Selects the operation performed by the microprocessor such as MOV,
ADD, INC, JMP, & etc.
It is either one or two byte in length for most machine language instruction.
 Encoding
A processes representing entire assembly instruction as a binary value or
hexadecimal format (machine perspective)
 Decoding
A process of converting hexadecimal format to assembly language
(human perspective)
8086 – 80486 Instruction
Format
Intel µP Instruction Encoding and Decoding

 Figure 1 – The format of the 8086 – 80486 Instruction a) 16-bit

instruction, b) 32-bit instruction
64-bit Mode (Pentium 4 -
Core2) Instruction Format
Intel µP Instruction Encoding and Decoding

Figure 2. The application of REX without scaled index

64-bit Mode (Pentium 4 -
Core2) Instruction Format
Intel µP Instruction Encoding and Decoding

Figure 3. The scaled-index byte and REX prefix for 64-bit operations.
8088 or 8086 Instruction
Format
Intel µP Instruction Encoding and Decoding
Byte 1 Byte 2 Byte 3 Byte 4 Byte 5 Byte 6

Low Disp. High Disp.

Low Data High Data
/ Data / Data
Opcode D W MOD REG R/M

Register operand / Registers to use in EA calculation

Register operand / Extension of opcode
Register mode / Memory mode with displacement length
Word / Byte operation
Direction is to Register / Direction is from Register
Operation code

 Figure 3 – 8088 or 8086 Instruction Format

Instruction Encoding
Intel µP Instruction Encoding and Decoding

 Instructions consist of:

operation (opcode) e.g. MOV
operands (number depends on operation)

 Operands specified using addressing modes

 Addressing mode may include addressing

information
Registers
Constant values
Variable
Instruction Encoding
Intel µP Instruction Encoding and Decoding

 Encoding of instruction must includes:

Opcode
Operands
Addressing information

 Encoding is process representing entire instruction as a binary

value (machine instructions)
Number of bytes needed depends on how much information must be
encoded .

 Instructions are encoded by assembler:

.OBJ file (link, then loaded by loader)

 Instructions are decoded by processor during execution cycle

Instruction Encoding
Intel µP Instruction Encoding and Decoding

 Override Prefixes
It is the first 2 bytes of a 32-bit instruction format
These bytes are not always used
Divided in Two Parts:
○ Address Size (AS) – modifies the size of the
address used the instruction and this byte is equal to
67h if in used.
 If the 80386/80486 is operating as 16-bit instruction mode
machine (real or protected mode) and 32-bit instruction, byte
is equal to 67h
 If the 80386/80486 is operating as 32-bit instruction mode
machine (real or protected mode) and 32-bit instruction, byte
is removed.
Instruction Encoding
Intel µP Instruction Encoding and Decoding

○ Operand Size (OS) - modifies the size of the

register.
 If the 80386 or 80486 is operating as 16-bit
instruction mode machine (real or protected mode)
and 32-bit instruction, byte is equal to 66h
 If the 80386 or 80486 is operating as 32-bit
instruction mode machine (real or protected mode)
and 32-bit instruction, byte is removed.

These toggle the size of the register and

operand address from 16-bit to 32-bit or vice
versa.
Instruction Encoding
Intel µP Instruction Encoding and Decoding

 FIRST BYTE: OPCODE, Direction (D), &

Word (W) bits
Opcode – select the operation performed by the
microprocessor (use the lists of opcodes)

 Direction (D) – indicates the flow of data

○ D = 1, data flow from (R/M) field to REG field (MEM
-> REG)
○ D = 0, if data flow from REG field to R/M field (REG
-> MEM)

Word (W) – determine the size of data or register

○ W = 1, 16- or 32-bit data width (word or dword)
○ W = 0, 8-bit data width (byte)
Instruction Encoding
Intel µP Instruction Encoding and Decoding

 W bit appear in most of the instruction but D bit mainly

appears with MOV and some other instructions

 D bit position may be replaced by “S" bit in ADD or SUB

instructions
 s = 1 for one (1) byte of immediate data is present which must
be sign-extended to produce a 16-bit operand
 s = 0 for two (2) bytes of immediate are present

 D bit is replaced by “C" bit in Shift and Rotate

instructions
 c = 1, this indicates whether CL is used for shift/rotate count
 c = 0, this indicates that CL is not used for shift/rotate count
How to Encode Instructions as
Binary Values?
Intel µP Instruction Encoding and Decoding
 SECOND BYTE: Mode (MOD or oo), Register
(REG or rrr), & Register/Memory (R/M or mmm)

 MODE (oo) field

○ This field specifies the addressing modes for selected
instruction.
○ This selects the type of addressing and whether a
displacement is present or with the selected instruction.
 MOD = 11, selects data addressing modes
 MOD = 00, 01, or 10, selects memory addressing modes

 REG (rrr) field

○ Field for register assignment

 R/M (mmm) (Register or Memory)

○ Field for register act as a memory or memory location
assignment.
Instruction Encoding
Intel µP Instruction Encoding and Decoding

 Figure 4 – Table for MOD field a) 16-bit, b) 32-

bit
Instruction Encoding
Intel µP Instruction Encoding and Decoding

 Figure 5 – REG field for w=0 & w=1

Instruction Encoding
Intel µP Instruction Encoding and Decoding

 Figure 6 – 16- and 32-bit R/M field, segment register field, and
scaled factor.
Instruction Encoding
Intel µP Instruction Encoding and Decoding

 Figure 7 – 8-, 16-, and 32-bit REG field and MEM field
Instruction Encoding (64-bit Mode)
Intel µP Instruction Encoding and Decoding

 Figure 8. The 64-bit

register and memory
designators for
RRRR and MMMM
Instruction Encoding (64-bit
Mode)
Intel µP Instruction Encoding and Decoding

 In the 64-bit mode, an additional prefix called

REX (Register EXtension) is added
 REX prefix, which is encoded as a 40H–4FH,
follows other prefixes and is placed immediately
before the opcode to modify it for 64-bit operation
 The purpose of the REX prefix is to modify the
REG and R/M fields in the second byte of the
instruction
 REX is needed to be able to address registers R8
through R15 (see Figure 6)
Instruction Encoding
Intel µP Instruction Encoding and Decoding

 Register Addressing
It uses the R/M field to specify a register instead of memory location

 Special Addressing Modes (SAM)

This addressing modes occurs whenever memory data are referenced by only the
displacement mode of addressing for 16-bit instructions.
○ MOV [1000h], DL
○ MOV NUMB, DL

MOD = 00 and R/M=110

Scaled-Index Byte
○ Indicates the additional forms of scaled-index addressing.
○ Occurs when R/M = 100
Examples (Encoding)
Intel µP Instruction Encoding and Decoding

 In Pentium 4 microprocessor, determine the equivalent

machine code and types of addressing mode of the
following assembly code:
1. MOV DX, AX
2. MOV DX, [BX + DI + 1234]
3. ADD AX, 1023
4. SUB DX, 1234
5. AND [BX + 12], AL
6. MOV EAX, [EBX + 4*ECX]
7. MOV [5267], DH
8. MOV DS, AX
9. MOV AX, [BX]
10. MOV [RBX], RDX
Examples (Decoding)
Intel µP Instruction Encoding and Decoding

 Given the following machine code (hex

code), determine the equivalent
assembly instruction for each. Assume
that the machine is 80286.

1. 0x8B923412
2. 0x81C17856
3. 0x2326