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Edt and Occ

This document discusses embedded deterministic test (EDT) techniques and on-chip clock controllers (OCC) used for testing integrated circuits. It describes: 1) How EDT uses lock-up latches between scan flops to fix timing problems and avoid large clock skews. These latches are inserted in scan chains from different clock domains or between flops in the same domain but at remote places. 2) How an OCC generates launch and capture pulses at speed during testing to enable at-speed transition testing of different clock domains on a chip. It uses a shift register and multiplexer logic to control clock pulses for transition and stuck-at fault testing. 3) How regular OCC structures work

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Kiruthika M
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2K views22 pages

Edt and Occ

This document discusses embedded deterministic test (EDT) techniques and on-chip clock controllers (OCC) used for testing integrated circuits. It describes: 1) How EDT uses lock-up latches between scan flops to fix timing problems and avoid large clock skews. These latches are inserted in scan chains from different clock domains or between flops in the same domain but at remote places. 2) How an OCC generates launch and capture pulses at speed during testing to enable at-speed transition testing of different clock domains on a chip. It uses a shift register and multiplexer logic to control clock pulses for transition and stuck-at fault testing. 3) How regular OCC structures work

Uploaded by

Kiruthika M
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PPTX, PDF, TXT or read online on Scribd
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EMBEDDED DETERMINISTIC TEST

Signals in EDT
Decompressor
Compressor
Compressor
Lockup latch
• Used for fixing timing problems especially for hold timing closure.
• Used to avoid large clock skew
• Lock-up latches are used in between the two scan flops

Where the lock up latch are used


• Scan chains from different clock domains
• Flops within same domain, but at remote places
Lock up latch
insertion
EDT test procedure waveforms
X blocking in the Compactor
X-Masking

• ONE HOT MASKING


• FLEXIBLE MASKING
1-hot masking
Flexible masking
FAULT ALIASING
ON CHIP CONTROLLER
Introduction
• On -chip clock controller is the logic inserted on the SOC for controlling
clocks during silicon testing for defects on ATE .
• OCC enables the AT-speed/Transition testing of the Logic by generating
two clock pulses at speed during capture phase
• OCC is a core logic used in the design to generate launch and capture
pulse.
• Modern SOC’s contain many blocks with multiple clock domains, and to
target transition test for each clock domain they requires one OCC per
clock domain.
• This makes additional area overhead in the actual SOC design.
Regular OCC structure
Internal structure of OCC
• This structure is designed to support both transition fault test(TFT=1)
and stuck at fault test(TFT=0).
• Shift register decides a delay between scan_en asserts low to launch
pulse of transition test
• When scan_en=1,the clkoutMux is connecting scan_clk to the clk_out.
• When scan_en=0,shift register starts shifting 1,pll_clk_en makes 1 to
CG to allow single pulse or double pulse from PLL depending on TFT.
Regular OCC Behaviour For
Transition test
Regular OCC Behaviour For Stuck at
Test
THANK YOU

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