Delays in Verilog

• Types of Delays:
• Inertial delay
• Transport delay
• Net delay
 Delays in Verilog (continued)
Inertial delay: intended to model gates and other devices that
do not propagate short pulses from the input to the output.
• An input pulse that is shorter than the delay of the
assignment does not propagate to the output. This feature is
called inertial delay.
• If a gate has an ideal inertial delay T, in addition to delaying
the input signals by time T, any pulse with a width less than
T is rejected.
 For example, if a gate has an inertial delay of 5 ns, a pulse
width 5ns would pass through, but a pulse of width 4.999 ns
would be rejected.
 Delays in Verilog (continued)

Transport delay: is intended to model the delay introduced by

wiring; it simply delays an input signal by the specified delay
time.
• In order to model this delay, a delay value must be specified
on the right-hand side of the statement.
 Delays in Verilog (continued)

Example of inertial and transport delays:

2-4
 Delays in Verilog (continued)
• The delay in the statement Z1 <= #10 X; is called intra-
assignment delay. The expression on the right hand side is
evaluated but not assigned to Z1 until the delay has elapsed
(also called delayed assignment).
• In a statement like #10 Z1 <= X; the delay of #10 elapses first
and then the expression is evaluated and assigned to Z1 (also
called delayed evaluation).
 Delays in Verilog (continued)

Net delay: refers to the time it takes from any driver on the net
to change value to the time when the net value is updated
and propagated further.

 The wire C2 has a net delay of 10 ns, C1 has a no delay.

 Delays in Verilog (continued)

There are inertial delays of 30ns for C1 in statement 1 and 20ns

for C 2 in statement 2, typically representative of gate delays.
After statement 2 processes its delay of 20 ns, the net delay of
10 ns is added to it. Figure indicates the difference between C1
and C2. C1 rejects all narrow pulses less than 30ns, whereas C2
rejects only pulses less than 20 units.
Delays in Verilog (continued)
 Delays in Verilog (continued)

The assign statement for D works with a 7ns inertial delay and
rejects any pulse below 7ns.
Hence D rejects the 3ns, 2ns and 5ns pulses in Y. The 3ns net
delay from the wire statement is added to the signal that comes
out from the assign statement.
In the case of E, pulses below 3 ns are rejected. Hence the 3 ns
pulse in Y passes through the assign statement for E, the 2 ns
pulse is rejected and the 5ns pulse is accepted. Hence the 3 ns
and 5 ns pulses get combined in the absence of the 2ns pulse to
yield output on E appears as a big 10ns pulse.
 Compilation, Simulation, and
Synthesis of Verilog Code
• Three phases in the simulation of Verilog code:
analysis (compilation), elaboration, and
simulation:

Compilation, Elaboration, and Simulation of Verilog Code

2-10
 Compilation, Simulation, and Synthesis of Verilog
Code (continued)
• Analysis (compilation): check source code; if a syntax or semantic
error occurs, then the compiler gives error message. Checks
references to libraries.
• Elaboration: creates a hierarchy of module instances, propagates
parameters among modules, makes drivers, and constructs a design
hierarchy.
• Simulation: consists of an initialization phase and actual simulation.
The initialization phase is used to give an initial value to the signal.
Events are kept on an event queue, ordered by simulation time.

Events can occur at different times. In order to keep track of the

events and to make sure they are processed in the correct order, the
events are kept on an event queue, ordered by simulation time.

2-11
 Compilation, Simulation, and Synthesis of Verilog
Code (continued)
• Verilog event queue is divided into five regions:
– 1. Active event region: events that occur at the current
simulation time.
– 2. Inactive event region: events that occur at the current
simulation time but that shall be processed after all the
active events are processed.
– 3. Non-blocking assign update region: events that have
been evaluated during some previous simulation time but
that shall be assigned at this simulation time after all the
active and inactive events are processed.
– 4. Monitor event region: events that shall be processed after
all the active, inactive, and non-blocking assign update
events are processed. 2-12
– 5. Future event region: events that occur at some future
simulation time are in this region.
When each Verilog statement is processed, events are added to the various
queue regions according to the following convention for each type of
statement:
i. Continuous assignment—evaluate RHS and add to active region as an
active update event.
ii. Procedural continuous assign—evaluate RHS and add to active region as
an update event.
iii. Blocking assignment with delay—compute RHS and put into future
event region for time after delay.
iv. Blocking assignment with no delay—compute RHS and put into inactive
region for current time.
v. Non-blocking assignment with no delay—compute RHS and schedule as
non-blocking assign update event for current time if zero delay.
vi. Non-blocking assignment with delay—compute RHS and schedule as
nonblocking assign update event for future time if zero delay.
vii. $monitor and $strobe system tasks—create monitor events for these
system tasks. (These events are continuously reenabled in every successive
time step.)
 Compilation, Simulation, and Synthesis of Verilog Code
(continued)

• Processing of all the active events is called a

simulation cycle; for each cycle these ordered
actions are performed:
– 1. Process all active update events.
– 2. Activate all inactive events for that time.
– 3. Activate all non-blocking assign update events and
process them.
– 4. Activate all monitor events and process them.
– 5. Advance time to the next event time and repeat from
step 1.

2-14
 Compilation, Simulation, and Synthesis of Verilog Code
(continued)

• Simulation and synthesis process:

Most important uses of Verilog is to synthesize or automatically create

hardware from a Verilog description. The synthesis software for Verilog
translates the Verilog code to a circuit description that specifies the needed
components and the connections between the components.

– A netlist is a list of required components and their

interconnections. 2-15
 Verilog Data Types and Operators

• Two main groups of data types:

– Variable:
• An abstraction of a data storage element.
• Stores a value from one assignment to the next. An
assignment statement in a procedure acts as a trigger that
changes the value in the data storage element.
• Examples: reg, time, integer, real, real-time.
– Net:
• Represent physical connections between structural entities,
such as gates.
• Generally, it does not store values. Instead, value is
determined by the values of its drivers.
• Examples: wire, tri, wand, wor.

2-16
 Verilog Data Types and Operators (continued)

• Bitwise and Logical Operators:

Operator type Operator symbols Operation performed
~ Bitwise NOT (1's complement)
& Bitwise AND
Bitwise | Bitwise OR
^ Bitwise XOR
~^ or ^~ Bitwise XNOR
! NOT
Logical && AND
|| OR

2-17
 Verilog Data Types and Operators (continued)

• Reduction and shift operators:

Operator type Operator symbols Operation performed
& Reduction AND
~& Reduction NAND
| Reduction OR
Reduction
~| Reduction NOR
^ Reduction XOR
~^ or ^~ Reduction XNOR
>> Logical right shift
<< Logical left shift
Shift
>>> Arithmetic right shift
<<< Arithmetic left shift

2-18
 Verilog Data Types and Operators (continued)

• Relational, logical and bitwise operators:

Operator type Operator symbols Operation performed
> Greater than
< Less than
Relational
>= Greater than or equal to
<= Less than or equal to
Logical and
== Logical equality
bitwise
!= Logical inequality
=== Case equality
!== Case inequality
2-19
 Verilog Data Types and Operators (continued)

• Arithmetic, concatenation, replication,

conditional operators:
Operator type Operator symbols Operation performed
+ Addition
- Subtraction
- 2's complement
Arithmetic
* Multiplication
/ Division
** Exponentiation
Concatenation {} Concatenation
Replication {{}} Replicate value m for n times
Conditional ?: Conditional
2-20