CSE 431

Computer Architecture

Fall 2005

Lecture 01:
Introduction
Mary Jane Irwin ( www.cse.psu.edu/~mji )
www.cse.psu.edu/~cg431

[Adapted from Computer Organization and Design,

Patterson & Hennessy, © 2005, UCB]

CSE431 L01 Introduction.1 Irwin, PSU, 2005

 Course Administration
 Instructor: Mary Jane Irwin [email protected]
348C IST Building Office Hrs: T 11:30-1:00
& W 12:30-2:00
 TA: Reetuparna Das
[email protected] 111A IST Office Hrs:
posted on the course web page
 Labs: Accounts on machines in 218 and 222 IST
 URL: www.cse.psu.edu/~cg431
 Text: Required: Computer Org and Design, 3rd
Edition, Patterson and Hennessy ©2005 Optional:
Superscalar Microprocessor Design Johnson, ©1991
 Slides:pdf on the course web page after lecture

CSE431 L01 Introduction.2 Irwin, PSU, 2005

 Grading Information
 Grade determinates
● Midterm Exam ~30%
- Tuesday, October 18th , 20:15 to 22:15, Location: 113 IST
● Final Exam ~30%
- ???, December ??th , ??:?? to ??:??, Location TBD
● Homeworks (5) ~30%
- Due at the beginning of class (or, if its code to be submitted
electronically, by 17:00 on the due date). No late assignments
will be accepted.
● Class participation & pop quizzes ~10%
 Let me know about midterm exam conflicts ASAP
 Grades will be posted on the course homepage
● Must submit email request for change of grade after
discussions with the TA (Homeworks/Quizzes) or instructor
(Exams)
● December 9th deadline for filing grade corrections; no
requests for grade changes will be accepted after this date
CSE431 L01 Introduction.3 Irwin, PSU, 2005
 Course Content
 Content
● Principles of computer architecture: CPU datapath and control
unit design (single-issue pipelined, superscalar, VLIW), memory
hierarchies and design, I/O organization and design, advanced
processor design (multiprocessors and SMT)

 Course goals
● To learn the organizational paradigms that determine the
capabilities and performance of computer systems. To
understand the interactions between the computer’s
architecture and its software so that future software designers
(compiler writers, operating system designers, database
programmers, …) can achieve the best cost-performance trade-
offs and so that future architects understand the effects of their
design choices on software applications.

 Course prerequisites
● CSE 331. Computer Organization and Design

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 What You Should Know - CSE271 and CSE331
 Basic logic design & machine organization
● logical minimization, FSMs, component design
● processor, memory, I/O

 Create, assemble, run, debug programs in an assembly

language
● MIPS preferred

 Create, simulate, and debug hardware structures in a

hardware description language
● VHDL or verilog

 Create, compile, and run C (C++, Java) programs

 Create, organize, and edit files and run programs on
Unix/Linux

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 Course Structure
 Design focused class
● Various homework assignments throughout the semester
● Simulation of architecture alternatives using SimpleScalar

 Lectures:
● 2 weeks review of the MIPS ISA and basic architecture
● 2 weeks pipelined datapath design issues
● 3 weeks superscalar/VLSI datapath design issues
● 2 week memory hierarchies and memory design issues
● 2 weeks I/O design issues
● 2 weeks multiprocessor design issues
● 1 week exams

CSE431 L01 Introduction.6 Irwin, PSU, 2005

 How Do the Pieces Fit Together?

Application
Operating
System
Compiler Firmware
Instruction Set
Architecture
Memory Instr. Set Proc. I/O system
system

Datapath & Control

Digital Design
Circuit Design

 Coordination of many levels of abstraction

 Under a rapidly changing set of forces
 Design, measurement, and evaluation
CSE431 L01 Introduction.7 Irwin, PSU, 2005
 How Do the Pieces Fit Together?

Application
Operating
CSE 411
System
CSE 421
Compiler Firmware
Instruction Set
Architecture
Memory Instr. Set Proc. I/O system
system
CSE 331 & 431 & 472
Datapath & Control
Digital Design CSE 271 & 471 & 478
CSE 447 & 477 Circuit Design

 Coordination of many levels of abstraction

 Under a rapidly changing set of forces
 Design, measurement, and evaluation
CSE431 L01 Introduction.8 Irwin, PSU, 2005
 Where is the Market?

Embedded
1200 1122 Desktop
Servers
1000 892
Millions of Computers

862
800

600 488
400 290

200 93 114 135 129 131

3 3 4 4 5
0
1998 1999 2000 2001 2002

CSE431 L01 Introduction.9 Irwin, PSU, 2005

 By the architecture of a system, I mean the complete and detailed
specification of the user interface. … As Blaauw has said,
“Where architecture tells what happens, implementation tells how
it is made to happen.”
The Mythical Man-Month, Brooks, pg 45

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 Instruction Set Architecture (ISA)
 ISA: An abstract interface between the hardware and the lowest
level software of a machine that encompasses all the information
necessary to write a machine language program that will run
correctly, including instructions, registers, memory access, I/O,
and so on.
“... the attributes of a [computing] system as seen by the
programmer, i.e., the conceptual structure and functional
behavior, as distinct from the organization of the data flows
and controls, the logic design, and the physical
implementation.” – Amdahl, Blaauw, and Brooks, 1964
● Enables implementations of varying cost and performance to run identical
software

 ABI (application binary interface): The user portion of the

instruction set plus the operating system interfaces used by
application programmers. Defines a standard for binary
portability across computers.

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 ISA Type Sales
Other
SPARC
1400
Hitachi SH
1200 PowerPC
Motorola 68K
1000
Millions of Processor

MIPS
800 IA-32
ARM
600

400
200
0
1998 1999 2000 2001 2002

PowerPoint “comic” bar chart with approximate values (see

text for correct values)
CSE431 L01 Introduction.12 Irwin, PSU, 2005
 Moore’s Law
 In 1965, Gordon Moore predicted that the number of
transistors that can be integrated on a die would double
every 18 to 24 months (i.e., grow exponentially with
time).

 Amazingly visionary – million transistor/chip barrier was

crossed in the 1980’s.
● 2300 transistors, 1 MHz clock (Intel 4004) - 1971
● 16 Million transistors (Ultra Sparc III)
● 42 Million transistors, 2 GHz clock (Intel Xeon) – 2001
● 55 Million transistors, 3 GHz, 130nm technology, 250mm2 die
(Intel Pentium 4) - 2004
● 140 Million transistor (HP PA-8500)

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 Processor Performance Increase

10000
Intel Pentium 4/3000
Performance (SPEC Int)

DEC Alpha 21264A/667

1000 DEC Alpha 21264/600 Intel Xeon/2000

100 DEC Alpha 5/500

DEC Alpha 4/266 DEC Alpha 5/300
DEC AXP/500 IBM POWER 100
10
HP 9000/750
IBM RS6000
1
1987 1989 MIPS
1991 M2000
1993 1995 1997 1999 2001 2003
SUN-4/260 MIPS M/120 Year

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 DRAM Capacity Growth

1000000 512M
256M
128M
100000 64M
Kbit capacity

16M
10000
4M
1000
1M

100 256K
64K
10
16K
1976 1978 1980 1982 1984 1986 1988 1990 1992 1994 1996 1998 2000 2002

Year of introduction

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 Impacts of Advancing Technology

 Processor
● logic capacity: increases about 30% per year
● performance: 2x every 1.5 years

 Memory
● DRAM capacity: 4x every 3 years, now 2x every 2 years
● memory speed: 1.5x every 10 years
● cost per bit: decreases about 25% per year

 Disk
● capacity: increases about 60% per year
CSE431 L01 Introduction.16 Irwin, PSU, 2005
 Impacts of Advancing Technology

 Processor
● logic capacity: increases about 30% per year
● performance: 2x every 1.5 years
ClockCycle = 1/ClockRate
500 MHz ClockRate = 2 nsec ClockCycle
1 GHz ClockRate = 1 nsec ClockCycle
4 GHz ClockRate = 250 psec ClockCycle
 Memory
● DRAM capacity: 4x every 3 years, now 2x every 2 years
● memory speed: 1.5x every 10 years
● cost per bit: decreases about 25% per year

 Disk
● capacity: increases about 60% per year
CSE431 L01 Introduction.17 Irwin, PSU, 2005
 Example Machine Organization
 Workstation design target
● 25% of cost on processor
● 25% of cost on memory (minimum memory size)
● Rest on I/O devices, power supplies, box

Computer
CPU Memory Devices

Control Input

Datapath Output

CSE431 L01 Introduction.18 Irwin, PSU, 2005

 PC Motherboard Closeup

CSE431 L01 Introduction.19 Irwin, PSU, 2005

 Inside the Pentium 4 Processor Chip

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 Example Machine Organization
 TI SuperSPARCtm TMS390Z50 in Sun SPARCstation20

MBus Module
SuperSPARC

Floating-point Unit
L2 CC DRAM
Integer Unit $ MBus Controller

Inst Ref Data L64852 MBus control

M-S Adapter STDIO
Cache MMU Cache
SBus serial
Store SCSI kbd
SBus mouse
Buffer DMA Ethernet audio
RTC
Bus Interface SBus Boot PROM
Cards Floppy

CSE431 L01 Introduction.21 Irwin, PSU, 2005

 MIPS R3000 Instruction Set Architecture
Registers
 Instruction Categories
● Load/Store
R0 - R31
● Computational
● Jump and Branch
● Floating Point
- coprocessor PC
● Memory Management HI
● Special LO

3 Instruction Formats: all 32 bits wide

OP rs rt rd sa funct

OP rs rt immediate

OP jump target

Q: How many already familiar with MIPS ISA?

CSE431 L01 Introduction.22 Irwin, PSU, 2005
 Next Lecture and Reminders
 Next lecture
● MIPS ISA Review
- Reading assignment – PH, Chapter 2

 Reminders
● HW1 out next lecture, due September 13th
● Evening midterm exam scheduled
- Tuesday, October 18th , 20:15 to 22:15, Location 113 IST
- Please let me know ASAP (via email) if you have a conflict

CSE431 L01 Introduction.23 Irwin, PSU, 2005