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Registers and Counters in Digital Design

This document discusses registers, counters, and their applications in digital circuits. It includes figures and tables describing 4-bit registers, shift registers, serial adders, and universal shift registers. It also covers binary and decimal counters, their logic diagrams and pin configurations. Standard integrated circuit chips for shift registers and counters are described through their pin configurations, logic diagrams, and function tables.

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Priyam bajpai
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625 views54 pages

Registers and Counters in Digital Design

This document discusses registers, counters, and their applications in digital circuits. It includes figures and tables describing 4-bit registers, shift registers, serial adders, and universal shift registers. It also covers binary and decimal counters, their logic diagrams and pin configurations. Standard integrated circuit chips for shift registers and counters are described through their pin configurations, logic diagrams, and function tables.

Uploaded by

Priyam bajpai
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PPT, PDF, TXT or read online on Scribd

CHAPTER 6

Registers and Counters

Digital Design: With an Introduction to the Verilog HDL, 5e by


M. Morris Mano and Michael D. Ciletti 1
FIGURE 6.1 Four‐bit register

Digital Design: With an Introduction to the Verilog HDL, 5e by


M. Morris Mano and Michael D. Ciletti 2
FIGURE 6.2 Four‐bit register with parallel load

Digital Design: With an Introduction to the Verilog HDL, 5e by


M. Morris Mano and Michael D. Ciletti 3
FIGURE 6.3 Four‐bit shift register

Digital Design: With an Introduction to the Verilog HDL, 5e by


M. Morris Mano and Michael D. Ciletti 4
FIGURE 6.4 Serial transfer from register A to register B

Digital Design: With an Introduction to the Verilog HDL, 5e by


M. Morris Mano and Michael D. Ciletti 5
TABLE 6.1 Serial‐Transfer Example

Digital Design: With an Introduction to the Verilog HDL, 5e by


M. Morris Mano and Michael D. Ciletti 6
FIGURE 6.5 Serial adder

Digital Design: With an Introduction to the Verilog HDL, 5e by


M. Morris Mano and Michael D. Ciletti 7
TABLE 6.2 State Table for Serial Adder

Digital Design: With an Introduction to the Verilog HDL, 5e by


M. Morris Mano and Michael D. Ciletti 8
FIGURE 6.6 Second form of serial adder

Digital Design: With an Introduction to the Verilog HDL, 5e by


M. Morris Mano and Michael D. Ciletti 9
FIGURE 6.7 Four‐bit universal shift register

Digital Design: With an Introduction to the Verilog HDL, 5e by


M. Morris Mano and Michael D. Ciletti 10
TABLE 6.3 Function Table for the Register of Fig. 6.7

Digital Design: With an Introduction to the Verilog HDL, 5e by


M. Morris Mano and Michael D. Ciletti 11
TABLE 6.4 For Shift Register IC-74LS95 Chip

Digital Design: With an Introduction to the Verilog HDL, 5e by


M. Morris Mano and Michael D. Ciletti 12
FIGURE 6.8 Pin configuration

Digital Design: With an Introduction to the Verilog HDL, 5e by


M. Morris Mano and Michael D. Ciletti 13
TABLE 6.5 Function Table

Digital Design: With an Introduction to the Verilog HDL, 5e by


M. Morris Mano and Michael D. Ciletti 14
FIGURE 6.9 Logic diagram

Digital Design: With an Introduction to the Verilog HDL, 5e by


M. Morris Mano and Michael D. Ciletti 15
TABLE 6.6 For Shift Register IC-74LS195 Chip

Digital Design: With an Introduction to the Verilog HDL, 5e by


M. Morris Mano and Michael D. Ciletti 16
FIGURE 6.10 Pin configuration

Digital Design: With an Introduction to the Verilog HDL, 5e by


M. Morris Mano and Michael D. Ciletti 17
TABLE 6.7 Function Table

Digital Design: With an Introduction to the Verilog HDL, 5e by


M. Morris Mano and Michael D. Ciletti 18
FIGURE 6.11 Logic diagram

Digital Design: With an Introduction to the Verilog HDL, 5e by


M. Morris Mano and Michael D. Ciletti 19
FIGURE 6.12 Four‐bit binary ripple counter

Digital Design: With an Introduction to the Verilog HDL, 5e by


M. Morris Mano and Michael D. Ciletti 20
TABLE 6.8 Binary Count Sequence

Digital Design: With an Introduction to the Verilog HDL, 5e by


M. Morris Mano and Michael D. Ciletti 21
FIGURE 6.13 State diagram of a decimal BCD counter

Digital Design: With an Introduction to the Verilog HDL, 5e by


M. Morris Mano and Michael D. Ciletti 22
FIGURE 6.14 BCD ripple counter

Digital Design: With an Introduction to the Verilog HDL, 5e by


M. Morris Mano and Michael D. Ciletti 23
FIGURE 6.15 Block diagram of a three‐decade decimal BCD counter

Digital Design: With an Introduction to the Verilog HDL, 5e by


M. Morris Mano and Michael D. Ciletti 24
TABLE 6.9 For Counter IC-74LS90 Chip

Digital Design: With an Introduction to the Verilog HDL, 5e by


M. Morris Mano and Michael D. Ciletti 25
FIGURE 6.16 Pin configuration

Digital Design: With an Introduction to the Verilog HDL, 5e by


M. Morris Mano and Michael D. Ciletti 26
FIGURE 6.17 Logic diagram

Digital Design: With an Introduction to the Verilog HDL, 5e by


M. Morris Mano and Michael D. Ciletti 27
TABLE 6.10(A) Mode Selection—Function Table

Digital Design: With an Introduction to the Verilog HDL, 5e by


M. Morris Mano and Michael D. Ciletti 28
TABLE 6.10(B) BCD Count Sequence—Function Table

Digital Design: With an Introduction to the Verilog HDL, 5e by


M. Morris Mano and Michael D. Ciletti 29
TABLE 6.11 For Counter IC-74LS93 Chip

Digital Design: With an Introduction to the Verilog HDL, 5e by


M. Morris Mano and Michael D. Ciletti 30
FIGURE 6.18 Pin configuration

Digital Design: With an Introduction to the Verilog HDL, 5e by


M. Morris Mano and Michael D. Ciletti 31
TABLE 6.12 Mode Selection

Digital Design: With an Introduction to the Verilog HDL, 5e by


M. Morris Mano and Michael D. Ciletti 32
FIGURE 6.19 Logic diagram

Digital Design: With an Introduction to the Verilog HDL, 5e by


M. Morris Mano and Michael D. Ciletti 33
TABLE 6.13 Function Table

Digital Design: With an Introduction to the Verilog HDL, 5e by


M. Morris Mano and Michael D. Ciletti 34
FIGURE 6.20 Pin configuration

Digital Design: With an Introduction to the Verilog HDL, 5e by


M. Morris Mano and Michael D. Ciletti 35
TABLE 6.14 Function Table

Digital Design: With an Introduction to the Verilog HDL, 5e by


M. Morris Mano and Michael D. Ciletti 36
FIGURE 6.21 Functional waveforms (typical clear, load, and count sequences)

Digital Design: With an Introduction to the Verilog HDL, 5e by


M. Morris Mano and Michael D. Ciletti 37
FIGURE 6.22 Logic diagram, IC-74192

Digital Design: With an Introduction to the Verilog HDL, 5e by


M. Morris Mano and Michael D. Ciletti 38
FIGURE 6.23 State diagram, IC-74192

Digital Design: With an Introduction to the Verilog HDL, 5e by


M. Morris Mano and Michael D. Ciletti 39
TABLE 6.15 Mode Select—Function Table, IC-74192*

Digital Design: With an Introduction to the Verilog HDL, 5e by


M. Morris Mano and Michael D. Ciletti 40
FIGURE 6.24 Pin configuration

Digital Design: With an Introduction to the Verilog HDL, 5e by


M. Morris Mano and Michael D. Ciletti 41
TABLE 6.16 Function Table

Digital Design: With an Introduction to the Verilog HDL, 5e by


M. Morris Mano and Michael D. Ciletti 42
FIGURE 6.25 Funtional waveforms (typical clear, load, and count sequences)

Digital Design: With an Introduction to the Verilog HDL, 5e by


M. Morris Mano and Michael D. Ciletti 43
FIGURE 6.26 Four‐bit synchronous binary counter

Digital Design: With an Introduction to the Verilog HDL, 5e by


M. Morris Mano and Michael D. Ciletti 44
FIGURE 6.27 Four‐bit up–down binary counter

Digital Design: With an Introduction to the Verilog HDL, 5e by


M. Morris Mano and Michael D. Ciletti 45
TABLE 6.17 State Table for BCD Counter

Digital Design: With an Introduction to the Verilog HDL, 5e by


M. Morris Mano and Michael D. Ciletti 46
TABLE 6.18 Function Table for the Counter of Fig. 6.28

Digital Design: With an Introduction to the Verilog HDL, 5e by


M. Morris Mano and Michael D. Ciletti 47
FIGURE 6.28 Four‐bit binary counter with parallel load

Digital Design: With an Introduction to the Verilog HDL, 5e by


M. Morris Mano and Michael D. Ciletti 48
FIGURE 6.29 Two ways to achieve a BCD counter using a counter with parallel load

Digital Design: With an Introduction to the Verilog HDL, 5e by


M. Morris Mano and Michael D. Ciletti 49
TABLE 6.19 State Table for Counter

Digital Design: With an Introduction to the Verilog HDL, 5e by


M. Morris Mano and Michael D. Ciletti 50
FIGURE 6.30 Counter with unused states

Digital Design: With an Introduction to the Verilog HDL, 5e by


M. Morris Mano and Michael D. Ciletti 51
FIGURE 6.31 Generation of timing signals

Digital Design: With an Introduction to the Verilog HDL, 5e by


M. Morris Mano and Michael D. Ciletti 52
FIGURE 6.32 Construction of a Johnson counter

Digital Design: With an Introduction to the Verilog HDL, 5e by


M. Morris Mano and Michael D. Ciletti 53
FIGURE 6.33 Simulation output of HDL Example 6.4

Digital Design: With an Introduction to the Verilog HDL, 5e by


M. Morris Mano and Michael D. Ciletti 54

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