8051 PPT For MSC
8051 PPT For MSC
CPU
External RAM, ROM, I/O
(No internal RAM, ROM, I/O ports in the CPU)
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Microcontroller
• A smaller computer on a CHIP
• On-chip RAM, ROM, I/O Ports, Timer, Serial Controller…
• Example: Motorola’s 6811, Intel’s 8051, Atmel 32
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Microprocessor vs. Microcontroller
Microprocessor Microcontroller
• CPU is stand-alone, RAM, • CPU, RAM, ROM, I/O and
ROM, I/O, timer are separate timer are all on a single chip
• Versatility • Single-purpose
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C based Embedded Systems
• Special purpose computer system usually completely inside
the device it controls
• Has specific requirements and performs pre-defined tasks
• Cost reduction compared to general purpose processor
• Different design criteria
– Performance
– Reliability
– Availability
– Safety
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Embedded Systems Examples
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Examples
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Harvard Architecture
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8051 CPU Operation
1. Features
2. Pin Diagram
3. Block Diagram
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8051 Microcontroller
• Intel introduced 8051, referred as MCS- 51, in
1981.
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Features of 8051
8 bit Processor
4KB Internal ROM
128 Bytes Internal RAM
Four 8 BIT I/O PORTS (32 I/O LINES)
Two 16 Bit Timers/Counters
On Chip Full Duplex UART for Serial Communication
5 Vector Interrupts ( 2 External, 3 Internal - Timer0,Timer1,Serial)
On Chip Clock Oscillator
16 bit Address bus
64k External Code Memory
64k External Data Memory
16-bit program counter to access external Code Memory and
16 bit Data Pointer to access external Data Memory
128 user defined flags
32 General Purpose Registers each of 8 bits
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8051 Family
• The 8051 is a subset of the 8052
• The 8031 is a ROM-less 8051
– Add external ROM to it
– You lose two ports, and leave only 2 ports for I/O operations
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Pin Diagram
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Block Diagram of 8051
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Separate read instructions for external data and code memory.
Internal code
External data memory
Memory
RAM
ROM or EPROM
64k
4k or up
0xFF
SFR(direct access)
128 bytes External code memory
ROM or EPROMext
64k
0x80
0x7F
0x30
0x2F
0x20
0x1F Register bank 0(R0-R7)
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XTAL1 and XTAL2 …..
• If you use a frequency source other than a crystal
oscillator, such as a TTL oscillator:
– It will be connected to XTAL1
– XTAL2 is left unconnected
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RST
• RESET pin is an input and is active high (normally low)
• Upon applying a high pulse to this pin, the microcontroller will
reset and terminate all activities
• This is often referred to as a power-on reset
• Activating a power-on reset will cause all values in the registers to
be lost
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EA’
• EA’, “external access’’, is an input pin and must be
connected to Vcc or GND
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PSEN’ and ALE
• PSEN, “program store enable’’, is an output pin
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I/O Port Pins
• The four 8-bit I/O ports P0, P1, P2
and P3 each uses 8 pins.
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Port 0
• Port 0 is also designated as AD0-AD7.
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Port 1 and Port 2
• In 8051-based systems with no external
memory connection:
– Both P1 and P2 are used as simple I/O.
• In 8051-based systems with external
memory connections:
– Port 2 must be used along with P0 to provide
the 16-bit address for the external memory.
– P0 provides the lower 8 bits via A0 – A7.
– P2 is used for the upper 8 bits of the 16-bit
address, designated as A8 – A15, and it cannot
be used for I/O.
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Port 3
• Port 3 can be used as input or output.
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Pin Description Summary
PIN TYPE NAME AND FUNCTION
Vss I Ground: 0 V reference.
Vcc I Power Supply: This is the power supply voltage for normal,
idle, and power-down operation.
P0.0 - P0.7 I/O Port 0: Port 0 is an open-drain, bi-directional I/O port. Port
0 is also the multiplexed low-order address and data bus
during accesses to external program and data memory.
P1.0 - P1.7 I/O Port 1: Port I is an 8-bit bi-directional I/O port.
P2.0 - P2.7 I/O Port 2: Port 2 is an 8-bit bidirectional I/O. Port 2 emits the
high order address byte during fetches from external
program memory and during accesses to external data
memory that use 16 bit addresses.
P3.0 - P3.7 I/O Port 3: Port 3 is an 8 bit bidirectional I/O port. Port 3 also
serves special features as explained.
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Pin Description Summary
PIN TYPE NAME AND FUNCTION
RST I Reset: A high on this pin for two machine cycles while the
oscillator is running, resets the device.
ALE O Address Latch Enable: Output pulse for latching the low byte
of the address during an access to external memory.
PSEN* O Program Store Enable: The read strobe to external program
memory. When executing code from the external program
memory, PSEN* is activated twice each machine cycle,
except that two PSEN* activations are skipped during
each access to external data memory.
EA*/VPP I External Access Enable/Programming Supply Voltage: EA*
must be externally held low to enable the device to fetch
code from external program memory locations. If EA* Is
held high, the device executes from internal program
memory. This pin also receives the programming supply
voltage Vpp during Flash programming. (applies for 89c5x
MCU's)
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General Block Diagram of 8051
Interrupt 4K Timer 0
128 B
Control ROM RAM Timer 1
CPU
Bus Serial
OSC 4 I/O Ports
Control Port
TXD RXD
P0 P1 P2 P3
Detailed Block Diagram
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8051
Memory
Space
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8051 Memory Structure
External
External
60K
64K 64K
SFR
EXT INT 4K
128
EA = 0 EA = 1 Internal
Program Memory Data Memory
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Internal RAM Structure
Direct
Addressing
Only
SFR [ Special Function
Direct & Registers]
Indirect
Addressing
128 Byte Internal RAM
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Special Function Registers [SFR]
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Program Status Word [PSW]
C AC F0 RS1 RS0 OV F1 P
Carry Parity
Auxiliary Carry User Flag 1
User Flag 0 Register Bank Select Overflow
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8051 instructions that affects flag
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128 Byte RAM
• There are 128 bytes of RAM in the 8051.
– Assigned addresses 00 to 7FH General Purpose
Area
• The 128 bytes are divided into 3 different
groups as follows:
BIT Addressable
1. A total of 32 bytes from locations 00 to 1F Area
hex are set aside for register banks and the 128 BYTE
stack. INTERNAL RAM
Reg Bank 3
2. A total of 16 bytes from locations 20H to 2FH
Reg Bank 2
are set aside for bit-addressable read/write Register Banks
memory. Reg Bank 1
3. A total of 80 bytes from locations 30H to 7FH Reg Bank 0
are used for read and write storage, called
scratch pad.
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8051 RAM with addresses
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8051 Register Bank Structure
Bank 3 R0 R1 R2 R3 R4 R5 R6 R7
Bank 2 R0 R1 R2 R3 R4 R5 R6 R7
Bank 1 R0 R1 R2 R3 R4 R5 R6 R7
Bank 0 R0 R1 R2 R3 R4 R5 R6 R7
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8051 Register Banks with address
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8051 Programming Model
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8051 Stack
• The stack is a section of RAM used by the CPU to store
information temporarily.
– This information could be data or an address
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Bit Addressable & Byte Addressable
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Single bit Instructions
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Bit Addressable Programming
• Example: Find out to which by each of the following bits
belongs. Give the address of the RAM byte in hex
(a) SETB 42H, (b) CLR 67H, (c) CLR 0FH (d) SETB 28H, (e) CLR 12, (f) SETB 05
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8051 Software Overview
1. Addressing Modes
2. Instruction Set
3. Programming
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8051 Addressing Modes
• The CPU can access data in various ways, which are
called addressing modes
1. Immediate
2. Register
3. Direct
4. Register indirect
5. External Direct
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Immediate Addressing Mode
• The source operand is a constant.
• The immediate data must be preceded by the pound sign, “#”
• Can load information into any registers, including 16-bit DPTR
register
– DPTR can also be accessed as two 8-bit registers, the high byte DPH and
low byte DPL
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Register Addressing Mode
• Use registers to hold the data to be manipulated.
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SFR Registers & their Addresses
MOV 0E0H,#55H ;is the same as
MOV A,#55H ;which means load 55H into A (A=55H)
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Stack and Direct Addressing Mode
• Only direct addressing mode is allowed for pushing or
popping the stack.
• PUSH A is invalid.
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Register Indirect Addressing Mode
• A register is used as a pointer to the data.
• Only register R0 and R1 are used for this purpose.
• R2 – R7 cannot be used to hold the address of an
operand located in RAM.
• When R0 and R1 hold the addresses of RAM locations,
they must be preceded by the “@” sign.
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Register Indirect Addressing Mode
• Write a program to copy the value 55H into RAM memory locations 40H
to 41H using (a) direct addressing mode, (b) register indirect addressing
mode without a loop, and (c) with a loop.
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Register Indirect Addressing Mode
• The advantage is that it makes accessing data dynamic
rather than static as in direct addressing mode.
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External Direct
• External Memory is accessed.
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8051 Instruction Set
• 8051 instructions have 8-bit opcode
• There are 256 possible instructions of which 255 are
• implemented
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MOV Instruction
• MOV destination, source ; copy source to destination.
ORG 500H
DATA1: DB 28 ;DECIMAL (1C in Hex)
DATA2: DB 00110101B ;BINARY (35 in Hex)
DATA3: DB 39H ;HEX
ORG 510H
DATA4: DB “2591” ; ASCII NUMBERS
ORG 518H
DATA6: DB “My name is Joe” ;ASCII CHARACTERS
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ADD Instruction and PSW
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ADD Instruction and PSW
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Multiplication of Unsigned Numbers
MUL AB ; A B, place 16-bit result in B and A
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Division of Unsigned Numbers
DIV AB ; divide A by B
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Checking an input bit
JNB (jump if no bit) ; JB (jump if bit = 1)
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Switch Register Banks
Internal code
External data memory
Memory
RAM
ROM or EPROM
64k
4k or up
0xFF
SFR(direct access)
128 bytes External code memory
ROM or EPROMext
64k
0x80
0x7F
0x30
0x2F
0x20
0x1F Register bank 0(R0-R7)
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8051
TIMERS
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8051 Timer/Counter
OSC ÷12
C /T 0 TLx THx TFx
(8 Bit) (8 Bit) (1 Bit)
C /T 1
T PIN
INTERRUPT
TR
Gate
INT PIN
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TMOD Register
GATE:
When set, timer/counter x is enabled, if INTx pin is high
and TRx is set.
When cleared, timer/counter x is enabled, if TRx bit set.
C/T*:
When set, counter operation (input from Tx input pin).
When cleared, timer operation (input from internal clock).
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TMOD Register
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TCON Register
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8051 Timer Modes
8051 TIMERS
Timer 0 Timer 1
Mode 0 Mode 0
Mode 1 Mode 1
Mode 2 Mode 2
Mode 3
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TIMER 0
OSC ÷12
C /T 0
TL0 TH0 TF0
C /T 1
T 0PIN
INTERRUPT
TR0
Gate
INT 0 PIN
TIMER 0 – Mode 0
13 Bit Timer / Counter
OSC ÷12
C /T 0 TL0 TH0 INTERRUPT
C /T 1 TF0
T 0PIN
(5 Bit) (8 Bit)
TR0
Gate
INT 0 PIN
OSC ÷12
C /T 0 TL0 TH0 INTERRUPT
C /T 1 TF0
T 0PIN
(8 Bit) (8 Bit)
TR0
Gate
INT 0 PIN
OSC ÷12
C /T 0 TL0 TH0 INTERRUPT
C /T 1 TF0
T 0PIN
(8 Bit) (8 Bit)
TR0
Gate Reload
INT 0 PIN
TH0
(8 Bit)
OSC ÷12
C /T 0 TL0 INTERRUPT
C /T 1 TF0
T 0PIN
(8 Bit)
TR0
Gate
INT 0 PIN
TR1
TIMER 1
OSC ÷12
C /T 0
TL1 TH1 TF1
C /T 1
T1PIN
INTERRUPT
TR1
Gate
INT 1 PIN
TIMER 1 – Mode 0
13 Bit Timer / Counter
OSC ÷12
C /T 0 TL1 TH1 INTERRUPT
C /T 1 TF1
T1PIN
(5 Bit) (8 Bit)
TR1
Gate
INT 1 PIN
OSC ÷12
C /T 0 TL1 TH1 INTERRUPT
C /T 1 TF1
T1PIN
(8 Bit) (8 Bit)
TR1
Gate
INT 1 PIN
OSC ÷12
C /T 0 TL1 TH1 INTERRUPT
C /T 1 TF1
T1PIN
(8 Bit) (8 Bit)
TR1
Gate Reload
INT 1 PIN
TH1
(8 Bit)
• Solution:
• The start bit is always one bit, but the stop bit can be
one or two bits
1. SBUF Register
2. SCON Register
3. PCON Register
•We can set it to high by software and thereby double the baud rate.
– Timer 0 Overflow.
– Timer 1 Overflow.
– Reception/Transmission of Serial Character.
– External Event 0.
– External Event 1.
--
• EA : Global enable/disable.
• --- : Reserved for additional interrupt hardware.
Serial Port
INT 0 Pin
Timer 1 Pin