Algorithmic Modeling of

State Machines
• Until now, we showed state machines being
modeled by data flow (using concurrent
statements)
• We will describe using algorithmic or procedural
form using conventional programming language
semantics
– process statements
– wait statements
– variable and signal assignments
– if and case statements
– loop statements
– while statements
 Sequential Style Syntax

[ process_label : ] PROCESS
[( sensitivity_list )]
-- process_declarations NO
BEGIN SIGNAL
process_statements DECLARATIONS!
END PROCESS [ process_label ];

Assignments are executed sequentially inside processes

 Sequential Statements
– {Signal,variable} assignments
– Flow control
• if <condition> then <statements> [elsif <statements>]
else <statements>
end if;
• for <range> loop <statements> end loop;
• while <condition> loop <statements> end loop;
• case <condition> is
when <value> => <statements>
when <value> => <statements>
when others => <statements>
end case;
– Wait on <signal> until <expression> for <time> ;
 Process Sequential Statements
– {Signal,variable} assignments
– Flow control
• if <condition> then <statements> [elsif <statements>]
else <statements>
end if;
• for <range> loop <statements> end loop;
• while <condition> loop <statements> end loop;
• case <condition> is
when <value> => <statements>
when <value> => <statements>
when others => <statements>
end case;
• signal and variable assignments
target_signal <= sources, signal, expression
target_variable := sources, signal, expression
– Wait on <signal> until <expression> for <time> ;
 WAIT-statement Syntax
• The wait statement causes the suspension of a
process statement or a procedure
• wait [sensitivity_clause] [condition_clause]
[timeout_clause ] ;
– sensitivity_clause ::= on signal_name { , signal_name }
• wait on CLOCK; wait on A, B;
– condition_clause ::= until boolean_expression
• wait until Clock = ‘1’; wait until A <= B;
– timeout_clause ::= for time_expression
• wait for 150 ns;
• Note:- any number of wait statement may be
placed in a process.
 Sensitivity-lists vs Wait-on-statement

Summation:
PROCESS( A, B, Cin)
BEGIN
Sum <= A xor B xor Cin;
END PROCESS Summation;

Summation: PROCESS
BEGIN
Sum <= A xor B xor Cin;
WAIT ON A, B, Cin;
END PROCESS Summation;

if you put a sensitivity list in a process,

you can’t have a wait statement!

if you put a wait statement in a process,

you can’t have a sensitivity list!
IF- vs CASE-statement Syntax

if (a=‘1’) then case (a&b) is

q <= ‘1’; when “00” =>
elsif (b=‘1’) then q <= ‘0’;
q <= ‘1’; when others =>
else q <= ‘1’;
q <=‘0’; end case;
end if;
 Case Statements
• Case statements allow
conditional execution of case expression is
statements according to when choices1 =>
a single expression
• The when others branch sequentialstatements
will be active if no 1
choices are matched when choices2 =>
• Choices must be
mutually exclusive! sequentialstatements
2
• A choice is a list of ...
discrete constant values
when others =>
• Case statements may be sequentialstatements
nested end case;
 Case Statements
architecture beh of mux is
begin
process
begin
case sel is
when “00” =>
dout <= din0;
when “01” =>
dout <= din1;
when “10” =>
dout <= din2;
when “11” =>
dout <= din3;
when others =>
dout <= “0”;
end case;
end;
end beh;
 Case Statements
type opcode is (add, sub, xor, nop, load, store);

architecture beh of alu is

Signal inst:opcode;
begin
process
begin
case inst is
when add => z <= a + b;
when sub => z <= a - b;
when xor => z <= a xor b;
when nop | load | store => z <= a;
end case;
end process;
end beh;

-- Note: The following two conditions are identical

when nop | load | store =>
when nop to store =>
Binary Counter State Diagram

S0
000 S1
S7 001
111

S6 S2
110 010

S5 S3
101 011

S4
100
 VHDL Model of Counter
architecture ALGORITHM of BIN_COUNTER is
begin
process
variable PRESENT_STATE: BIT_VECTOR(2 downto 0) := B”111”;
begin
case PRESENT_STATE is
when B”000” => PRESENT_STATE := B”001”;
when B”001” => PRESENT_STATE := B”010”;
when B”010” => PRESENT_STATE := B”011”;
when B”011” => PRESENT_STATE := B”100”;
when B”100” => PRESENT_STATE := B”101”;
when B”101” => PRESENT_STATE := B”110”;
when B”110” => PRESENT_STATE := B”111”;
when B”111” => PRESENT_STATE := B”000”;
end case;
Z <= PRESENT_STATE after 10 nsec;
wait until (CLK = ‘1’;
end process;
end ALGORITHM;
 FOR- Vs WHILE-statement Syntax

for i in 0 to 9 loop For is considered to be a

q(i) <= a(i) and b(i); combinational circuit by some
synthesis-tools. Thus, it cannot have
end loop; a wait statement to be synthesised.

i:=0; While is considered to be an FSM

while (i<9) loop by some synthesis-tools. Thus, it
q <= a(i) and b(i); needs a wait statement to be
WAIT ON clk UNTIL clk=‘1’; synthesised
end loop;
Case Statements
architecture beh of mux is
begin
process
begin
case sel is
when “00” =>
dout <= din0;
when “01” =>
dout <= din1;
when “10” =>
dout <= din2;
when “11” =>
dout <= din3;
when others =>
dout <= “0”;
end case;
end;
end beh;
 Two Full Adder
Processes
Summation:
PROCESS( A, B, Cin)
BEGIN
Sum <= A XOR B XOR Cin;
END PROCESS Summation;
A
Sum
B
Cout
Cin
Carry:
PROCESS( A, B, Cin)
BEGIN
Cout <= (A AND B) OR
(A AND Cin) OR
(B AND Cin);
END PROCESS Carry;
 Complete Architecture
ARCHITECTURE example OF full_adder IS
-- Nothing needed in declarative block...
BEGIN

Summation: PROCESS( A, B, Cin)

BEGIN
Sum <= A XOR B XOR Cin;
END PROCESS Summation;

Carry: PROCESS( A, B, Cin)

BEGIN
Cout <= (A AND B) OR
(A AND Cin) OR
(B AND Cin);
END PROCESS Carry;

END example;
Alternate Carry Process

Carry: PROCESS( A, B, Cin)

BEGIN
IF ( A = ‘1’ AND B = ‘1’ ) THEN
Cout <= ‘1’;
ELSIF ( A = ‘1’ AND Cin = ‘1’ ) THEN
Cout < = ‘1’;
ELSIF ( B = ‘1’ AND Cin = ‘1’ ) THEN
Cout <= ‘1’;
ELSE
Cout <= ‘0’;
END IF;
END PROCESS Carry;
 Sequential …?
11/0

00/0 01/0
01/1 10/0
S1
10/1 S0 11/1

00/1
NS: process(p_state, n_state,x,y)
Begin
entity seq is State: process Case p_state is
port (x, y, clk: in std_logic; Begin When S0 =>

s:out STD_LOGIC); Wait until (clk=‘1’); If ((t=“00”)or (t=“01”) or (t=“10”)

then
ARCHITECTURE algo of seq is p-_state <= n_state
N_state<=P_state;
Signal t:std_logic_vector(1 downto 0); End process Else
type state_type is (S0, S1); N_state<= S1;
Signal P_state, N_state: state_type:=S0; End if;
Begin
T<= x& y;
 NS: process(p_state, n_state,t)
OP: process(p_state, n_state,t)
Begin
Begin
Case p_state is
Case p_state is
When S0 =>
When S0 =>
If ((t=“00”)or (t=“01”) or (t=“10”) then
If ((t=“00”) or (t<=“11’)) then
N_state<=P_state;
S<= ‘0’;
Else
Elsif ((t=“01”) or (t=“10”) then
N_state<= S1;
S<=‘1’;
End if;
End if;
When S1 =>
When S1 =>
If ((t=“00”) or (t=“11)) then
If ((t=“11”)or (t=“01”) or (t=“10”) then
S<= ‘1’;
N_state<=P_state;
Elsif ((t=“01”) or (t=“10”) then
Else
S<=‘0’;
N_state<= S0;
End if;
End if;
End case
 Ones Count Circuit Interface
Specification
1 entity ONES_CNT is
2 port ( A : in BIT_VECTOR(2 downto 0);
C : out BIT_VECTOR(1 downto 0));
-- Function Documentation of ONES_CNT
D -- (Truth Table Form)
O -- ____________________
C -- | A2 A1 A0 | C1 C0 |
U -- |-----------------|------------- |
M
E
-- | 0 0 0 | 0 0 |
N -- | 0 0 1 | 0 1 |
T -- | 0 1 0 | 0 1 |
A -- | 0 1 1 | 1 0 |
T -- | 1 0 0 | 0 1 |
I
-- | 1 0 1 | 1 0 |
O
N -- | 1 1 0 | 1 0 |
-- | 1 1 1 | 1 1 |
-- |__________ |________|
3 end ONES_CNT;
 Ones Count Circuit Architectural Body:
Behavioral (Truth Table)
Architecture Truth_Table of ONES_CNT is
begin
Process(A) -- Sensitivity List Contains only Vector A
begin
CASE A is
WHEN "000" => C <= "00";
WHEN "001" => C <= "01";
WHEN "010" => C <= "01";
WHEN "011" => C <= "10";
WHEN "100" => C <= "01";
WHEN "101" => C <= "10";
WHEN "110" => C <= "10";
WHEN "111" => C <= "11";
end CASE;
end process;
end Truth_Table;
 Ones Count Circuit Architectural Body:
Behavioral (Algorithmic)
Architecture Algorithmic of ONES_CNT is
begin
Process(A) -- Sensitivity List Contains only Vector A
Variable num: INTEGER range 0 to 3;
begin
num :=0;
For i in 0 to 2 Loop
IF A(i) = '1' then
num := num+1;
end if;
end Loop;
--
-- Transfer "num" Variable Value to a SIGNAL
--
CASE num is
WHEN 0 => C <= "00";
WHEN 1 => C <= "01";
WHEN 2 => C <= "10";
WHEN 3 => C <= "11";
end CASE;
end process;
end Algorithmic;
 Divide-by-8 Counter
Entity counter IS
Generic (td_cnt: TIME := 8 NS);
PORT (reset, clk: IN BIT; counting: OUT BIT :=‘0’);
Constant limit: INTEGER :=8;
END counter ;
Architecture behavioral OF counter IS
Begin
Process(clk)
Variable count: INTEGER := limit;
Begin
IF (clk = ‘0’ AND clk’Event ) THEN
IF reset = ‘1’ THEN
count := 0 ;
ELSE
IF count < limit THEN
count:= count+1;
END IF;
END IF;
IF (count /= limit) Then counting <= ‘0’ AFTER td_cnt;
ELSE counting <= ‘1’ AFTER td_cnt;
END IF;
END IF;
END process;
END behavioral ;
 Example, Memory Model
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;

entity mem is
port( read,write,clk : in std_logic;
address : in unsigned(7 downto 0);
data : inout std_logic_vector(7 downto 0);
end entity;

architecture beh of mem is

type mem_array is array(7 downto 0) of std_logic_vector(7 downto 0);
begin
process(clk)
variable memory : mem_array;
begin
if rising_edge(clk) then
if read='1' then
data <= memory(conv_integer(address));
elsif write='1' then
memory(conv_integer(address)) := data;
end if;
end if;
end process;
end architecture beh;
 Example of shift register
library ieee ;
use ieee.std_logic_1164.all;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity sipo is
generic (n: NATURAL:=8);
port(a:in std_logic;
b:in std_logic_vector(n-1 downto 0);
s:in std_logic;
q: buffer std_logic_vector(n-1 downto 0);
clk:in std_logic);
end sipo;

architecture rtl of sipo is

begin
p0: process (clk)
variable reg: std_logic_vector (n-1 downto 0);
begin
if rising_edge(clk) then
case s is
when '1' =>
reg := b;
when '0' =>
reg:= a & reg(n-1 downto 1);
when others => null;
end case;
q<=reg;
end if;
end process p0;
end rtl;
 State Machines
type state is (state0, state1);
architecture beh of stt_mach is
signal curstate, nextstate : state; x=1
begin
update: process(x,y,curstate)
begin
case curstate is
when state0 =>
if x=0 then state0
z=1
nextstate <= state1;
elsif x=1 then
nextstate <= state0;
end if;
when state1 =>
if x=1 then
nextstate <= state1;
elsif x=0 then x=0
nextstate <= state0;
x=0
end if;
end case;
end process update;
process(clk, reset)
begin
state1
if reset=‘1’ then z=0
curstate <= state’left;
else
if rising_edge(clk) then
curstate <= nextstate;
end if;
end if; x=1
end process;
end beh;
 State Machines
• For the output simply use another process:
-- A typical Moore machine (output depends on current state only)
gen_output: process(curstate) -- activate when state changes
begin
case curstate is
when state0 =>
z <= 1;
when state1 =>
z <= 0;
end case;
end process gen_output;

-- A Mealy machine (output depends on current state and inputs)

gen_output: process(curstate,x,y) -- activate when state changes
begin
case curstate is
when state0 =>
z <= 1;
when state1 =>
z <= 0;
end case;
end process gen_output;
 Controller Description
• Moore Sequence Detector
– Detection sequence is 110
x IF 110 found on x
Then Z gets ‘1’ z
clk Else z gets ‘0’
End

1 1 1 0
0
S0 S1 S2 S3
/0 /0 /0 /1

0 1

0
 VHDL Description of Moore 110 Sequence
Detector
ENTITY moore_110_detector IS
PORT (x, clk : IN BIT; z : OUT BIT);
END moore_110_detector;
ARCHITECTURE behavioral OF moore_110_detector IS
TYPE state IS (S0,S1,S2,S3);
SIGNAL current : state := S0;
BEGIN
PROCESS(clk)
BEGIN
IF (clk = '1' AND CLK’Event) THEN
CASE current IS
WHEN S0=>
IF x = '1' THEN current <= S1;
ELSE current <= S0; END IF;
WHEN S1 =>
IF x = '1' THEN current <= S2;
ELSE current <= S0; END IF;
WHEN S2=>
IF x = '1' THEN current <= S2;
ELSE current <= S3; END IF;
WHEN S3=>
IF x = '1' THEN current <=S1;
ELSE current <= S0; END IF;
END CASE;
END IF;
END PROCESS;
z <='1' WHEN current = S3 ELSE '0';
END behavioral;