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William Stallings Computer Organization and Architecture 8th Edition Internal Memory

The document summarizes different types of semiconductor memory, including RAM, ROM, PROM, EPROM, and EEPROM. It discusses the characteristics of dynamic RAM and static RAM, such as volatility, memory cell structure, read/write mechanisms, and usage. The document also covers ROM organization, error correction techniques, and memory packaging.

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Sheikh Zain
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59 views

William Stallings Computer Organization and Architecture 8th Edition Internal Memory

The document summarizes different types of semiconductor memory, including RAM, ROM, PROM, EPROM, and EEPROM. It discusses the characteristics of dynamic RAM and static RAM, such as volatility, memory cell structure, read/write mechanisms, and usage. The document also covers ROM organization, error correction techniques, and memory packaging.

Uploaded by

Sheikh Zain
Copyright
© © All Rights Reserved
Available Formats
Download as PPT, PDF, TXT or read online on Scribd
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William Stallings

Computer Organization
and Architecture
8th Edition

Chapter 5
Internal Memory
Semiconductor Memory Types
Memory Type Category Erasure Write Mechanism Volatility

Random-access
Read-write memory Electrically, byte-level Electrically Volatile
memory (RAM)

Read-only
Masks
memory (ROM)
Read-only memory Not possible

Programmable
ROM (PROM)

Erasable PROM
UV light, chip-level
(EPROM) Nonvolatile

Electrically

Electrically Erasable Read-mostly memory


Electrically, byte-level
PROM (EEPROM)

Flash memory Electrically, block-level


Semiconductor Memory
• RAM
—Misnamed as all semiconductor memory is
random access
—Read/Write
—Volatile
—Temporary storage
—Static or dynamic
Memory Cell Operation
Dynamic RAM
• Bits stored as charge in capacitors
• Charges leak
• Need refreshing even when powered
• Simpler construction
• Smaller per bit
• Less expensive
• Need refresh circuits
• Slower
• Main memory
• Essentially analogue
—Level of charge determines value
Dynamic RAM Structure
DRAM Operation
• Address line active when bit read or written
— Transistor switch closed (current flows)
• Write
— Voltage to bit line
– High for 1 low for 0
— Then signal address line
– Transfers charge to capacitor
• Read
— Address line selected
– transistor turns on
— Charge from capacitor fed via bit line to sense amplifier
– Compares with reference value to determine 0 or 1
— Capacitor charge must be restored
Static RAM
• Bits stored as on/off switches
• No charges to leak
• No refreshing needed when powered
• More complex construction
• Larger per bit
• More expensive
• Does not need refresh circuits
• Faster
• Cache
• Digital
—Uses flip-flops
Stating RAM Structure
Static RAM Operation
• Transistor arrangement gives stable logic
state
• State 1
—C1 high, C2 low
—T1 T4 off, T2 T3 on
• State 0
—C2 high, C1 low
—T2 T3 off, T1 T4 on
• Address line transistors T5 T6 is switch
• Write – apply value to B & compliment to
B
• Read – value is on line B
SRAM v DRAM
• Both volatile
—Power needed to preserve data
• Dynamic cell
—Simpler to build, smaller
—More dense
—Less expensive
—Needs refresh
—Larger memory units
• Static
—Faster
—Cache
Read Only Memory (ROM)
• Permanent storage
—Nonvolatile
• Microprogramming (see later)
• Library subroutines
• Systems programs (BIOS)
• Function tables
Types of ROM
• Written during manufacture
—Very expensive for small runs
• Programmable (once)
—PROM
—Needs special equipment to program
• Read “mostly”
—Erasable Programmable (EPROM)
– Erased by UV
—Electrically Erasable (EEPROM)
– Takes much longer to write than read
—Flash memory
– Erase whole memory electrically
Organisation in detail
• A 16Mbit chip can be organised as 1M of
16 bit words
• A bit per chip system has 16 lots of 1Mbit
chip with bit 1 of each word in chip 1 and
so on
• A 16Mbit chip can be organised as a 2048
x 2048 x 4bit array
—Reduces number of address pins
– Multiplex row address and column address
– 11 pins to address (211=2048)
– Adding one more pin doubles range of values so x4
capacity
Refreshing
• Refresh circuit included on chip
• Disable chip
• Count through rows
• Read & Write back
• Takes time
• Slows down apparent performance
Typical 16 Mb DRAM (4M x 4)
Packaging
Interleaved Memory
• Collection of DRAM chips
• Grouped into memory bank
• Banks independently service read or write
requests
• K banks can service k requests
simultaneously
Error Correction
• Hard Failure
—Permanent defect
• Soft Error
—Random, non-destructive
—No permanent damage to memory
• Detected using Hamming error correcting
code
Error Correcting Code Function

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