Introduction to CPLDs

Complex Programmable
Logic Devices

CSET 4650
Field Programmable Logic Devices

Dan Solarek
 Hierarchy of Logic Implementations
Logic

Standard
ASIC
Logic

Programmable
Gate Cell-Based Full Custom
today’s focus Logic Devices
Arrays ICs ICs
(FPLDs)

SPLDs CPLDs
(e.g., PALs) FPGAs

Acronyms Common Resources

SPLD = Simple Prog. Logic Device Configurable Logic Blocks (CLB)
PAL = Prog. Array of Logic Memory Look-Up Table (LUT)
CPLD = Complex PLD AND-OR planes
Simple gates
FPGA = Field Prog. Gate Array
Input / Output Blocks (IOB)
ASIC = Application Specific IC
Bidirectional, latches, inverters, pullup/pulldowns
Interconnect or Routing
Local, internal feedback, and global
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PAL Architecture
Recall the PAL device
we studied earlier
PAL16L8
16 inputs
32 input AND gates
up to 8 output
functions
Outputs are selectable
between OR/NOR

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Why CPLDs?
For larger applications, we could simply increase the number
of inputs and outputs in a conventional SPLD …
e.g., 16V8 → 20V8 → 22V10
why not keep this trend going → 32V16 → 128V64 ?
Problems:
n times the number of inputs and outputs requires n2 as much chip
area → too costly
logic gets slower as number of inputs to AND array increases
Solution:
multiple PLDs with a relatively small (fast) programmable
interconnect
less general than a single large PLD, but we can use software to
partition our design into smaller PLD blocks

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5
6
CPLDs
To create a CPLD device:
put a lot of Simple PLDs on the same chip
add “wires” between them whose connections can be
programmed (interconnect)
use fuse/EEPROM technology for the connections
Comparing CPLDs to FPGAs:
CPLD devices are faster, cheaper and have fewer gates
than FPGAs
Meant for interfacing rather than heavy computation
Include built-in flash memory
FPGAs need external memory

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PLCC Package With Socket

d
boar
ir cuit Plastic Leaded Chip Carrier
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Pri 8
Examples of CPLDs

Examples of CPLDs and high pin count package types

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Programming Complex PLDs
Some CPLDs are programmed using a PAL
programmer
this method becomes inconvenient for devices with
hundreds of pins
A second method of programming
solder the device to its printed circuit board
program it with a serial data stream from a personal
computer
the CPLD decodes the data stream and configures itself to
perform a specified logic function

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Programming Complex PLDs
Each manufacturer has a proprietary name for its
CPLD programming system.
Lattice calls it "in-system programming"
Proprietary systems are beginning to give way to a
standard from the Joint Test Action Group (JTAG)

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CPLD Packaging and Programming
(a) a CPLD in a
Quad Flat Pack (a)
(QFP) IC package
(b) Set up for
(a) CPLD in a Quad Flat Pack (QFP) package
programming the
PCB-mounted
To computer
CPLD using JTAG (b)

Printed
circuit board

(b) JTAG programming 12

CPLD Structure and Alternate Names
A Simple PLD (or SPLD) is
usually a PLA or a PAL
A Complex PLD (CPLD) is
an arrangement of multiple
SPLD-like blocks on a single
chip.
Alternative names include:
enhanced PLD (EPLD)
superPAL
megaPAL

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Structure of a CPLD: A Closer Look

I/O block

I/O block
PAL-like PAL-like
block block

Interconnection wires
I/O block

I/O block
PAL-like PAL-like
block block
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Section of a CPLD

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CPLD Size Comparison
A CPLD is just a collection of individual PLDs on a single
chip
accompanied by a programmable interconnection structure that allows
the PLDs to be hooked up to each other on-chip
in the same way that a clever designer might do with discrete PLDs
off-chip
For an SPLD, the chip area for n times as much logic is close
to n2 … (think about an n x n square)
For a CPLD, the chip area for n times as much logic is only n
times the area of a single PLD plus the area of the
programmable interconnect structure.

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CPLDs
Rising densities/performance and declining prices
become a good choice for many applications
100K gates today
250K+ gates in near future
Low-density CPLD (32 macrocells/44 pins)
5ns logic delays
High-density CPLD (128 macrocells/100 pins)
7.5ns logic delays

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CPLD Components
Primitive or basic cells
The term “primitive” usually refers to simple logic cells
such as NAND, NOR, FLIP-FLOPs, LATCHES,
BUFFERS, and INVERTERS
Macrocells
also called 'megacells' or 'supercells'
offer diversified functions
range from a shift register to a complex microprocessor

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 Who makes the CPLDs?

Manufacturer CPLD Products URL

Altera MAX 5000, 7000 & 9000 www.altera.com

Altmel ATF & ATV www.atmel.com
Cypress FLASH370, Ultra37000 www.cypress.com
Lattice ispLSI 1000 to 8000 www.latticesemi.com
Philips XPLA www.philips.com
Vantis MACH 1 to 5 www.vantis.com
Xilinx XC9500 www.xilinx.com

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Lect #14 Rissacher EE365
Xilinx
Product
XC7000 Series
XC7200 Series
– Each block has 9 macrocells
– Each macrocells includes two OR-gates
– Each OR-gates is input to a two-bit ALU
XC7300 Series : Enhanced version of 7200
XC9500 Series
In-system programmability

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 Xilinx: XC9500 Device Family
XC9536 XC9572 XC95108 XC95144 XC95216 XC95288
Macrocells 36 72 108 144 216 288
Usable Gates 800 1,600 2,400 3,200 4,800 6,400
Registers 36 72 108 144 216 288
t PD (ns) 5 7.5 7.5 7.5 10 10
t SU (ns) 3.5 4.5 4.5 4.5 6.0 6.0
t CO (ns) 4.0 4.5 4.5 4.5 6.0 6.0
f CNT (MHz) 100 125 125 125 111.1 111.1
f SYSTEM (MHz) 100 83.3 83.3 83.3 66.7 66.7

Note:
f CNT = Operating frequency for 16-bit counters
f SYSTEM = Internal operating frequency for general purpose system designs spanning
multiple FBs.

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Xilinx
Architecture of Xilinx 9500 CPLDs

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Xilinx: XC9500 Device Family
Each XC9500 device is a subsystem consisting of multiple
Function Blocks (FBs) and I/O Blocks (IOBs) fully
interconnected by the FastCONNECT switch matrix.
The IOB provides buffering for device inputs and outputs.
Each FB provides programmable logic capability with 36
inputs and 18 outputs.
The FastCONNECT switch matrix connects all FB outputs
and input signals to the FB inputs. For each FB, 12 to 18
outputs (depending on package pin-count) and associated
output enable signals drive directly to the IOBs.

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Xilinx: XC9500 Device Family

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Xilinx: XC9500 Device Family
Each Function Block is comprised of 18 independent
macrocells, each capable of a combinatorial or registered
function. The FB also receives global clock, output enable,
and set/reset signals.
The FB generates 18 outputs that drive the FastCONNECT
switch matrix. These 18 outputs and their corresponding
output enable signals also drive the IOB.
Logic within the FB is implemented using a sum-of-products
representation. Thirty-six inputs provide 72 true and
complement signals into the programmable AND-array to
form 90 product terms. Any number of these product terms,
up to the 90 available, can be allocated to each macrocell by
the product term allocator.

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Function Block,
Each Function Block, as shown in Figure 2 is comprised of
18 independent macrocells, each capable of implementing
a combinatorial or registered function .
The FB also receives global clock, output enable, and set/reset signals.
The FB generates 18 outputs that drive the FastCONNECT switch
matrix.
These 18 outputs and their corresponding output enable signals also drive
the IOB.
Logic within the FB is implemented using a sum-of-products
representation. Fifty-four inputs provide 108 true and complement
signals into the programmable AND-array to form 90 product terms.
Any number of these product terms, up to the 90 available, can be
allocated to each macrocell by the product term allocator.

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Xilinx: XC9500 Device Family
Each FB (except for the XC9536) supports local feedback
paths that allow any number of FB outputs to drive into its
own programmable AND-array without going outside the FB.
These paths are used for creating very fast counters and state
machines where all state registers are within the same FB.

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Xilinx: XC9500: Macrocell
Each XC9500 macrocell may be individually configured for a
combinatorial or registered function. The macrocell and
associated FB logic is shown in Figure 3.
Five direct product terms from the AND-array are available for
use as primary data inputs (to the OR and XOR gates) to
implement combinatorial functions, or as control inputs
including clock, set/reset, and output enable. The product term
allocator associated with each macrocell selects how the five
direct terms are used.
The macrocell register can be configured as a D-type or T-type
flip-flop, or it may be bypassed for combinatorial operation.
Each register supports both asynchronous set and reset
operations. During power-up, all user registers are initialized to
the user-defined preload state (default to 0 if unspecified).

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Xilinx: XC9500 Device Family

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Xilinx: XC9500 : global control signals
All global control signals are available to each individual macrocell,
including clock, set/reset, and output enable signals.
As shown in Figure 4, the macrocell register clock originates from either
of three global clocks or a product term clock. Both true and complement
polarities of a GCK pin can be used within the device. A GSR input is
also provided to allow user registers to be set to a user-defined state.

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Product term allocator
The product term allocator controls how the five direct
product terms are assigned to each macrocell. For example,
all five direct terms can drive the OR function as shown in
Figure 5
The product term allocator can re-assign other productb terms
within the FB to increase the logic capacity of a macrocell
beyond five direct terms. Any macrocell requiring additional
product terms can access uncommitted product terms in other
macrocells within the FB. Up to 15 product terms can be
available to a single macrocell with only a small incremental
delay of tPTA, as shown in Figure 6.

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Product Term Allocation With 15 ProductTerms

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Note that the incremental delay affects only the
product terms in other macrocells. The timing of the
direct product terms is not changed.

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The product term allocator can re-assign product
terms from any macrocell within the FB by
combining partial sums of products over several
macrocells, as shown in Figure 7.
In this example, the incremental delay is only
2*TPTA.
All 90 product terms are available to any macrocell,
with a maximum incremental delay of 8*TPTA.

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Product Term Allocation Over Several Macrocells

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The internal logic of the product term allocator

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Xilinx: XC9500 Device Family
The FastCONNECT switch matrix connects signals to the FB
inputs, as shown in Figure 9. All IOB outputs (corresponding
to user pin inputs) and all FB outputs drive the
FastCONNECT matrix. Any of these (up to a FB fan-in limit
of 54) may be selected, through user programming, to drive
each FB with a uniform delay.
The FastCONNECT switch matrix is capable of combining
multiple internal connections into a single wired-AND output
before driving the destination FB. This provides additional
logic capability and increases the effective logic fan-in of the
destination FB without any additional timing delay. This
capability is available for internal connections originating
from FB outputs only. It is automatically invoked by the
development software where applicable.

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Xilinx: XC9500 switch matrix

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Xilinx: XC9500 Device Family
The I/O Block (IOB) interfaces between the internal
logic and the device user I/O pins. Each IOB
includes an input buffer, output driver, output enable
selection multiplexer, and user programmable
ground control. See Figure 10 for details.
The input buffer is compatible with standard 5 V
CMOS, 5 V TTL and 3.3 V signal levels. The input
buffer uses the internal 5 V voltage supply (V
CCINT ) to ensure that the input thresholds are
constant and do not vary with the V CCIO voltage.

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Xilinx: XC9500 Device Family

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Xilinx: XC9500 ISP
XC9500 devices are programmed in-system via a
standard 4-pin JTAG protocol. In-system
programming offers quick and efficient design
iterations and eliminates package handling.
The Xilinx development system provides the
programming data sequence using a Xilinx
download cable, a third-party JTAG development
system, JTAG-compatible board tester, or a simple
micro-processor interface that emulates the JTAG
instruction sequence.

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ISP

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Xilinx: XC9500 Device Family
XC9500 devices can also be programmed by the
XilinxHW130 device programmer as well as third-
party programmers. This provides the added
flexibility of using pre-programmed devices during
manufacturing, with an in-system programmable
option for future enhancements.

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Xilinx: XC9500 Device Family
XC9500 devices incorporate advanced data security features which
fully protect the programming data against unauthorized reading or
inadvertent device erasure/reprogramming. Table 3 shows the four
different security settings available.
The read security bits can be set by the user to prevent the internal
programming pattern from being read or copied. When set, they also
inhibit further program operations but allow device erase. Erasing the
entire device is the only way to reset the read security bit.
The write security bits provide added protection against accidental
device erasure or reprogramming when the JTAG pins are subject to
noise, such as during system power-up. Once set, the write-
protection may be deactivated when the device needs to be
reprogrammed with a valid pattern.
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Pin-Locking Capability
The capability to lock the user defined pin assignments during
design iteration depends on the ability of the architecture
to adapt to unexpected changes.
The XC9500XL
devices incorporate architectural features that enhance the
ability to accept design changes while maintaining the same
pinout.

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Power-Up Characteristics

During power-up, the XC9500XL device I/Os may be undefined until

VCCINT rises above 1 Volt. This time period is called the subthreshold
region, as transistors have not yet fully turned on. If VCCIO is powered
before or simultaneously with VCCINT, I/Os may drive during this
voltage transition range.
If VCCIO is powered after VCCINT has passed through the
subthreshold region, I/Os will be in 3-state with a weak pull-up until
VCCINT reaches the threshold of the User Operation state
(approximately 2.5V).
When VCCINT reaches this point, user registers are initialized (typically
within 200 μs) after which I/Os will assume the behavior determined by
the user pattern, as shown in Figure
If the device is in the erased state (before any user pattern is
programmed), the device outputs remain disabled with weak pull-up. The
JTAG pins are enabled to allow the device to be programmed at any time.
All devices are shipped in the erased state from the factory.
If the device is programmed, the device inputs and outputs take on their
configured states for normal operation. The JTAG pins are enabled to
allow device erasure or boundary- scan tests at any time. 46
Device Behavior During Power-up

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