Parallel Processors and Cluster Systems: Gagan Bansal IME Sahibabad
Parallel Processors and Cluster Systems: Gagan Bansal IME Sahibabad
Cluster Systems
Gagan Bansal
IME Sahibabad
Distributed Memory
Architecture
P6 P6 P6 P6 P6 P6 P6 P6
L2 L2 L2 L2 L2 L2 L2 L2
MEMORY MEMORY
L3 L3
1GB/Sec
To Other Node
The Cache memory ( called level 2, o L2) runs at
processor speed and is accessible with each
processor cycle. Requested data not found in cache is
read from main memory and copied into L2 cache.
Data not found in a main memory of the requesting
motherboard must be retrieved from a “far” memory
of another SHV motherboard via a fast interconnect
that can move data at a speed of 1GB/Sec. The
interconnect maintains a level 3 (L3) cache to store
data requested from far memory location. The
multiple cache hierarchy (L2 and L3) help reduce the
penalty for accessing data from adjacent nodes.
COMA