What happens if the drain-source

voltage exceeds VGS − VTH ?

ID does not follow the parabolic
behavior for VDS > VGS − VTH

1
Local density of the inversion-
layer charge is proportional to
VGS − V(x) − VTH
Thus, if V(x) approaches
VGS − VTH then Qd (x) drops
to zero.
If VDS is slightly greater than VGS − VTH,
then the inversion layer stops at x ≤ L
How does the device conduct current
in the presence of pinch-off?

2
As the electrons approach the pinch-off point (where Qd → 0), their
velocity rises tremendously (v = I /Qd ).
Upon passing the pinch-off point, the electrons simply shoot through
the depletion region near the drain junction and arrive at the drain
terminal.

3
The integral on the left-hand side of (2.7) must be taken from x = 0 to
x = L’, where L’ is the point at which Qd drops to zero, and that on the
right from V(x) = 0 to V(x) = VGS − VTH. As a result,
“square-law”

The drain-source voltage must be equal to

or greater than the overdrive voltage
VDS > VGS − VTH
The choice of the overdrive and
hence VD,sat translates to a certain
voltage “headroom” for the signal
swings in the circuit: the larger the
VD,sat , the less headroom is
available for the signals.
4
 represent the “large-signal”
behavior of NMOS devices
For PMOS devices

The negative sign appears here because we assume that ID flows from
the drain to the source, whereas holes flow in the reverse direction.

current source connected between the drain and the source

Chap04-Sedra Smith
5
 On a VDS-VGS plane, show the
regions of operation of an NMOS
transistor.

Since the value of VDS with respect to VGS − VTH determines the region
of operation, we draw the line VDS = VGS − VTH in the plane, as shown
in Fig. 2.18. If VDS > VGS − VTH then the region above
the line corresponds to saturation

6
Chap04-Sedra Smith
7
 VDS = VGS − VTH
VD - VS = VG - VS − VTH
VD = VG − VTH
VTH = VG − VD
VD > VG − VTH
VTH > VG − VD
pinch-off occurs

Chap04-Sedra Smith
11
 MOS Transconductance
Define a figure of merit that indicates how well a device converts
a voltage to a current

We express gm in 1/Ω or in siemens (S)

Interestingly, gm in the saturation region is equal to the inverse of Ron

in the deep triode region.

Chap04-Sedra Smith
12
13
The ID and VGS − VTH terms in the above gm equations are bias values.
For example, a transistor with W/L = 5 μm/0.1 μm and biased at ID =
0.5 mA may exhibit a transconductance of (1/200 ).
If a signal is applied to the device, then ID and VGS − VTH and hence gm
vary, but in small-signal analysis, we assume that the signal amplitude
is small enough that this variation is negligible.
For a PFET, the transconductance in the saturation region is
expressed as

Chap04-Sedra Smith
14
Example 2.3
For the arrangement shown in Fig. 2.21, plot the transconductance as a
function of VDS.

As VDS decreases from infinity

So long as VDS ≥ Vb − VTH, M1 is in saturation, ID is relatively

constant, and so is gm.

15
 ID gm
62.5E-6 250.0E-6

μnCox (μA/V2) W/L VTH Vb Vb-VTH

50 10 0.3 0.8 0.5
0.000300

0.000250

0.000200

0.000150

0.000100

0.000050 gm VDS

0.000000
0 0.2 0.4 0.6 0.8 1 1.2
Second-Order Effects Our analysis of the MOS structure has thus
far entailed various simplifying assumptions,
Body Effect
some of which are not valid in many analog
circuits.

we surmise that the device continues to operate properly, but some of

its characteristics may change.

17
Suppose VS = VD = 0, and VG is somewhat less than VTH
Depletion region is formed under the gate but no inversion layer exists

If VB becomes more negative then what happens?

As VB drops and Qd increases, VTH also increases
This phenomenon is called the “body effect” or the “back-gate effect.”

ϒ denotes the body-effect coefficient, and VSB is the source-bulk

potential difference.
The value of ϒ typically lies in the range of 0.3 to 0.4 V1/2
Example 2.4 In Fig. 2.24(a), plot the drain current if VX varies from
−∞ to 0. Assume VTH0 = 0.3 V, ϒ = 0.4 V1/2, and 2φF = 0.7 V.
If VX is sufficiently negative,
the threshold voltage of M1
exceeds 1.2 V and the device
is off.

19
 1.00E-04
9.00E-05
8.00E-05
7.00E-05

Vx vs ID 6.00E-05
5.00E-05
4.00E-05
3.00E-05
2.00E-05
1.00E-05
0.00E+00
-5 -4 -3 CMOS IC by Razavi Ch02
-2 -1 0 20
The bulk potential, Vsub, need not change:
if the source voltage varies with respect to Vsub, the same
phenomenon occurs.
Fig. 2.25(a), first ignoring body effect.
We note that as Vin varies, Vout closely follows the input because the
drain current remains equal to I1.
We can write

Vin − Vout is constant if I1 is constant

Now suppose that the substrate is tied to ground and body effect is
significant.
Now the potential difference between the source and the bulk
increases, raising the value of VTH.

Equation implies that Vin − Vout must increase

so as to maintain ID constant.
Body effect is usually undesirable.
The change in the threshold voltage often
complicates the design of analog (and even
digital) circuits.
Device technologists balance Nsub and Cox to
obtain a reasonable value for γ .

Nsub is the doping density of the substrate

22
Example 2.5 Equation (2.23) suggests that if VSB becomes negative,
then VTH decreases. Is this correct?

If the bulk voltage of an NMOS device rises above its source voltage,
VTH falls below VTH0.
This observation proves useful in low-voltage design, where the
performance of a circuit may suffer due to a high threshold voltage;
one can bias the bulk to reduce VTH.
Unfortunately, this is not straightforward for NFETs because they
typically share one substrate, but it can readily be applied to
individual FETs.
Channel-Length Modulation
The actual length of the channel gradually decreases as the potential
difference between the gate and the drain decreases.
Lꞌ is in fact a function of VDS.

This effect is called “channel-length modulation.”

Assuming a first-order relationship between ΔL/L and VDS, such as

ΔL/L = λVDS, we have, in saturation,

where λ is the “channel-length

modulation coefficient.”
 where λ is the “channel-
length modulation
The parameter λ represents coefficient.”
the relative variation in
length for a given increment
in VDS. Thus, for longer
channels, λ is smaller.
Example 2.6 Is there channel-length modulation in the triode region?
No channel modulation

at the edge of the triode region

observe a discontinuity in
the equations
This discrepancy is removed
in more complex models of MOSFETs

26
28
Example 2.7 Keeping all other parameters constant, plot the ID/VDS
characteristic of a MOSFET for L = L1 and L = 2L1.
ΔL/L = λVDS
If the length is doubled, the slope of ID vs. VDS is divided by four

This is true only if VGS − VTH

is constant.)
A larger L gives a more ideal
current source while
degrading the current
capability of the device.
W may need to be increased proportionally.
Double W to restore ID to its original value, the slope also doubles.
For required ID doubling the length reduces the slope by a factor of 2.
That is, we always consider VGS − VTH as the current-defining
parameter.
29
Sub-threshold Conduction In our analysis of the MOSFET, we have
assumed that the device turns off abruptly as VGS drops below VTH.
In reality, for VGS ≈ VTH, a “weak” inversion layer still exists and some
current flows from D to S.
Even for VGS < VTH, ID is finite, but it exhibits an exponential
dependence on VGS . Called “sub-threshold conduction,” this effect can
be formulated for VDS greater than roughly 100 mV as
where I0 is proportional to W/L, ξ > 1 is a non-ideality
factor, and VT = kT/q. “weak inversion.”
With typical values of ξ, at room
temperature, VGS must decrease
by approximately 80 mV for ID to
decrease by one decade.
For example, if a threshold of 0.3 V is
chosen in a process to allow low-voltage
operation, then when VGS is reduced to zero, the drain current
decreases by only a factor of
For example, if the transistor carries about 1 μA for VGS = VTH and we
have 100 million such devices, then they draw 18 mA when they are
nominally off.
Especially problematic in large circuits such as memories, sub-threshold
conduction can result in significant power dissipation (or loss of analog
information).
If a MOS device conducts for VGS < VTH, then how do we define the
threshold voltage?
Indeed, numerous definitions have been proposed.
One possibility is to extrapolate, on a logarithmic vertical scale, the
weak inversion and strong inversion characteristics and consider their
intercept voltage as the threshold (Fig. 2.28).
In physics, the electron volt (symbol eV; also written electronvolt[) is
a unit of energy equal to approximately 1.602×10−19 Joules (Si unit J).
By definition, it is the amount of energy gained by the charge of a
single electron moved across an electric potential difference of
one volt.
Thus it is 1 volt (1 joule per coulomb, 1 J/C) multiplied by the electron
charge (1 e, or 1.602176565×10−19 C).
Therefore, one electron volt is equal to 1.602176565×10−19 J.
Historically, the electron volt was devised as a standard unit of
measure through its usefulness in electrostatic particle accelerator
sciences because a particle with charge q has an energy E=qV after
passing through the potential V;
1 eV = 1.602176487×10−19 J (the conversion factor is numerically
equal to the elementary charge expressed in coulombs).
For BJT

bandgap energy, is 1.12 electron volt (eV) for silicon

Is it possible to achieve an arbitrarily high transconductance by
increasing W while maintaining ID constant?
if W increases while ID remains constant
then VGS → VTH and the device enters the sub-threshold region.
MOSFETs are still inferior to bipolar
transistors in this respect.
At what overdrive voltage can we say the transistor goes from strong
inversion to weak inversion?

For ξ ≈ 1.5, this amounts to about 80 mV.

Dependence of ID upon VGS suggests to achieve a higher gain.
However, since such conditions are met only by a large device width
or low drain current, the speed of subthreshold circuits is severely
limited.
34
Example 2.8 Examine the behavior of a MOSFET as the drain “current
density,” ID/W, varies.
For a given drain current and device width, how do we determine the
region of operation?
We must consider the equations for both strong and weak inversion:

for a given current and W/L, we

must obtain VGS from both

select the lower

value of VGS
If ID remains constant and W increases, VGS falls and the device goes
from strong inversion to weak inversion.
Voltage Limitations
A MOSFET experiences various undesirable effects if its terminal
voltage differences exceed certain limits (if the device is “stressed”).
At high gate-source voltages, the gate oxide breaks down irreversibly,
damaging the transistor.
In short-channel devices, an excessively large drain-source voltage
widens the depletion region around the drain so much that it touches
that around the source, creating a very large drain current.
(This effect is called “punchthrough”).
Even without breakdown, MOSFETs’ characteristics can change
permanently if the terminal voltage differences exceed a specified
value. Such effects are described in Chapter 17.
MOS Device Models MOS Device Layout
For example, W/L is chosen to set the transconductance or other
circuit parameters while the minimum L is dictated by the process.
In addition to the gate, the source and drain areas must be defined
properly as well. one or more “contact
windows” must be
opened in each region,

Example 2.9
Draw the layout of the circuit shown in Fig. 2.30(a).

37
MOS Device Capacitances

Decomposition of S/D junction

capacitance into bottom-plate and
sidewall components.

38
(1) the oxide capacitance between the gate and the channel,
C1 = WLCox;
(2) the depletion capacitance between the channel and the substrate,
C2 = WL √qϵsi Nsub/(4φF ); and
(3) the capacitance due to the overlap of the gate poly with the source
and drain areas, C3 and C4. Owing to fringing electric field lines, C3
and C4 cannot be simply written as WLDCox, and are usually obtained
by more elaborate calculations. The overlap capacitance per unit
width is denoted by Cov and expressed in F/m (or fF/μm).We simply
multiply Cov by W to find the gate-source and gate-drain overlap
capacitances.
(4) The junction capacitance between the source/drain areas and the
substrate. As shown in Fig. 2.32(b), this last capacitance is
decomposed into two components:

39
the bottom-plate capacitance associated with the bottom of the
junction, Cj , and the sidewall capacitance due to the perimeter of
the junction, Cjsw. The distinction is necessary because different
transistor geometries yield different area and perimeter values for
the S/D junctions. We specify Cj and Cjsw as capacitance per unit
area (in F/m2) and unit length (in F/m), respectively. Thus, Cj is
multiplied by the S/D area, and Cjsw by the S/D perimeter. Note that
each junction capacitance can be expressed as Cj = Cj0/[1 +
VR/(B)]m, where VR is the reverse voltage across the junction, B is
the junction built-in potential, and m is a power typically in the
range of 0.3 and 0.4.
41
42
Example 2.10 Calculate the source and drain junction capacitances of
the two structures shown in Fig. 2.33.

Fig. 2.33(b) exhibits

less drain junction
capacitance than
that in Fig. 2.33(a)
while providing the
same W/L.

43
If the device is off, CGD = CGS = CovW, and
the gate-bulk capacitance consists of the series combination of the
gate-oxide capacitance and the depletion-region capacitance
[Fig.2.32(a)], i.e

If the device is in the deep triode region, i.e., if S and D have

approximately equal voltages, then the gate-channel capacitance,
WLCox, is divided equally between the gate and source terminals and
the gate and drain terminals (Fig. 2.34). This is because a change of
ΔV in the gate voltage draws equal amounts of charge from S and D.
Thus,

44
Let us now consider CGD and CGS. If in saturation, a MOSFET exhibits a
gate-drain capacitance roughly equal to WCov. As for CGS, we note that
the potential difference between the gate and the channel varies
from VGS at the source to VTH at the pinch-off point, resulting in a
nonuniform vertical electric field in the gate oxide as we travel from
the source to the drain. It can be proved that the equivalent
capacitance of this structure, excluding the gate-source overlap
capacitance, equals (2/3)WLCox . Thus, CGS = 2WLeffCox/3+WCov. The
behavior of CGD and CGS in different regions of operation is plotted in
Fig. 2.34. Note that the above equations do not provide a smooth
transition from one region of operation to another, creating
convergence difficulties in simulation programs. This issue is revisited
in Chapter 17. The gate-bulk capacitance is usually neglected in the
triode and saturation regions because the inversion layer acts as a
“shield” between the gate and the bulk. In other words, if the gate
voltage varies, the charge is supplied by the source and the drain
rather than the bulk.
Example 2.11
Sketch the capacitances of M1 in Fig. 2.35 as VX varies from zero to 3 V.
Assume that VTH = 0.3 V and λ = γ = 0.

and CFB is maximum

The value of CNB is independent of VX. As VX exceeds 1
V, the role of the source and drain is exchanged [Fig.
2.36(a)], eventually bringing M1 out
of the triode region for VX ≥ 2 V−0.3 V. The variation of
the capacitances is plotted in Figs. 2.36(b) and (c).

46
MOS Small-Signal Model

where it is assumed that λVDS << 1

Output resistance, rO , is important ?
47
Now recall that the bulk potential influences the threshold voltage and
hence the gate-source overdrive.
That is, the bulk behaves
as a second gate.
In the saturation region, gmb can be
expressed as

typically
around 0.25.
incremental body effect becomes
less pronounced as VSB increases.

48
We note that folding reduces the gate resistance by a factor of four.

49
Shown in Fig. 2.39, the complete small-signal model includes the
device capacitances as well.

50
Example 2.12
Sketch gm and gmb of M1 in Fig. as a function of the bias current I1.

The dependence of gmb upon I1 is less straightforward. As I1 increases,

VX decreases, and so does VSB.
PMOS Small-Signal Model

52
53
54
NMOS Versus PMOS Devices
In most CMOS technologies, PMOS devices are quite inferior to NMOS
transistors.
For example, due to the lower mobility of holes,
μpCox ≈ 0.5μnCox, yielding low current drive and transconductance.
Moreover, for given dimensions and bias currents, NMOS transistors
exhibit a higher output resistance, providing more ideal current
sources and higher gain in amplifiers.
For these reasons, incorporating NFETs rather than PFETs wherever
possible is preferred.
Long-Channel Versus Short-Channel Devices
In this chapter, we have employed a very simple view of MOSFETs so
as to understand the basic principles of their operation.
Most of our treatment is valid for “long-channel” devices, e.g.,
transistors having a minimum length of a few microns.
Many of the relationships derived here must be reexamined and
revised for short-channel MOSFETs.
Furthermore, the SPICE models necessary for simulation of today’s
devices are much more sophisticated than the Level 1 model.
For example, the intrinsic gain, gmrO, calculated from the device
parameters in Table 2.1 is much higher than actual values.
These issues are studied in Chapter 17.
We begin with a simplistic view of devices.
The key point is that the simple model provides a great deal of
intuition that is necessary in analog design.
We often encounter a trade-off between intuition and rigor, and our
approach is to establish the intuition first and gradually complete our
understanding so as to achieve rigor as well.
FinFETs
This device exhibits superior
performance as channel lengths fall
below approximately 20 nm.
In fact, FinFET I/V characteristics
are closer to square-law behavior,
making our simple large-signal
mode relevant again.
The equivalent channel width is
therefore equal to the sum of the fin’s
width, WF , and twice its height, HF :
W = WF +2HF .
Typically, WF ≈ 6 nm and HF ≈ 50 nm.

57
Behavior of a MOS Device as a Capacitor
Inversion layer begins to form for VGS ≈ VTH.
We also noted that for 0 < VGS < VTH, the
device operates in the subthreshold region.

Let us begin with a very negative gate-source voltage.

As VGS rises, the density of holes at the
interface falls, a depletion region begins to
form under the oxide, and the device enters
weak inversion.
In this mode, the capacitance consists of the
series combination of Cox and Cdep.
Finally, as VGS exceeds VTH, the oxide-silicon
interface sustains a channel and the unit-area
capacitance returns to Cox. Figure 2.46 plots
the behavior.
59