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How To Find AMAT - Final - Question

The document describes the cache hierarchy of a system with separate L1 instruction and data caches and a unified L2 cache. It provides details on the size, mapping, block size, write policy, and miss rates of each cache. It also provides statistics on instruction mix and dirty blocks in L2 cache. Finally, it poses three questions about calculating memory access time and indexing bits for each cache.

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286 views

How To Find AMAT - Final - Question

The document describes the cache hierarchy of a system with separate L1 instruction and data caches and a unified L2 cache. It provides details on the size, mapping, block size, write policy, and miss rates of each cache. It also provides statistics on instruction mix and dirty blocks in L2 cache. Finally, it poses three questions about calculating memory access time and indexing bits for each cache.

Uploaded by

shfks
Copyright
© © All Rights Reserved
Available Formats
Download as PPTX, PDF, TXT or read online on Scribd
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How to find AMAT

In a multi-level cache

An Example
Qualcomm Snapdragon Flagship SoCs 2018-2019
SoC Snapdragon 845 Snapdragon 855
CPU 1x Kryo 485 Gold (A76 derivative)
4x Kryo 385 Gold (A75
@ 2.84GHz 1x512KB pL2
derivative)
@ 2.8GHz 4x256KB L2
3x Kryo 485 Gold (A76 derivative)
@ 2.42GHz 3x256KB pL2
4x Kryo 385 Silver (A55
derivative)
4x Kryo 485 Silver (A55 derivative)
@ 1.80GHz 4x128KB L2
@ 1.80GHz 4x128KB pL2
2MB L3
2MB sL3 @ 1612MHz
GPU Adreno 630 Adreno 640 @ 585MHz
Memory 4x 16-bit CH @ 1866MHz 4x 16-bit CH @ 2092MHz
LPDDR4x LPDDR4X
29.9GB/s 33.4GB/s
3MB system cache 3 MB system level cache
Mfc.
10nm LPP 7nm LPE
Process
Let us look at Snapdragon 800 chipset cache
• ARM cortex A 15 processor has 32kB of instruction
and 32kB of data L1 cache. L2 cache is a unified
cache of size 4 MB

• Qualcomm krait 800 has three levels of cache; L0, L1


& L2 Samsung Galaxy 6
Cache Size Architecture Frequency
L0 4KB + 4KB Direct mapped Core
L1 16KB+16KB 4-way set associative Core
L2 1MB (Dual core) or 8-way set associative 1.3GHz max
2MB (Quad core)
General Formula

• AMAT = Time for a hit + miss rate X miss penalty


• What if we have a two level cache, L1 and L2?

AMAT = Time for L1 hit +


miss rate of L1 x { time for L2 hit +
(miss rate of L2 x L2 miss penalty)}
Memory Hierarchy

L1
I$
L2
Processor Unified Main
L1 Cache Memory
D$
Problem Statement

A certain system with a 500 MHz clock uses a Harvard


architecture (separate data and instruction caches) at the first
level, and a unified second-level cache. The first-level data
cache is a direct-mapped, write-through, writes-allocate cache
with 8 Kbytes of data total and 8-Byte blocks, and has a
perfect write buffer (never causes any stalls).

The first-level instruction cache is a direct-mapped cache


with 4KBytes of data total and 8-byte blocks. The second-
level cache is a two-way set associative, write-back, write-
allocate cache with 2MBytes of data total and 32-Byte
blocks.
Contd:

The first-level instruction cache has a miss-rate of 2%. The


first-level data cache has a miss-rate of 15%. The unified
second-level cache has a local miss rate of 10% (i.e. the
miss rate for all accesses going to the second-level cache).
Assume that 40% of all instructions are data memory
accesses; 60% of those are loads, and 40% are stores.
Assume that 50% of the blocks in the second-level cache
are dirty at any time. Assume that there is no optimization for
fast reads on an L1 or L2 cache miss.
Contd.
All first-level cache hits cause no stalls. The second-level hit
time is 10 cycles (That means that the L1 miss-penalty,
assuming a hit in the L2 cache, is 10 cycles). Main memory
access time is 100 cycles to the first bus width of data; after
that, the memory system can deliver consecutive bus widths
of data on each following cycle. Outstanding, non-
consecutive memory requests can not overlap; an access to
one memory location must complete before an access to
another memory location can begin. There is a 128-bit bus
from memory to the L2 cache, and a 64-bit bus from both L1
caches to the L2 cache. Assume that the TLB never causes
any stalls.
Questions…
1. What fraction of all data memory references cause a main
memory access (main memory is accessed before the
memory request is satisfied)? First show the equation,
then the numeric result.

2. How many bits are used to index each of the caches ie


Instruction, Data and L2 ?

3. What is the average memory access time in cycles


(including instructions and data memory references)? First
show the equation, then the numeric result. Hint: don’t
forget to consider dirty lines in the L2 cache.
Problem Statement (easy to read)
A certain system with a 500 MHz clock uses a Harvard
architecture (separate data and instruction caches) at the first
level, and a unified second-level cache. The first-level data
cache is a direct-mapped, write-through, writes-allocate cache
with 8 Kbytes of data total and 8-Byte blocks, and has a
perfect write buffer (never causes any stalls).

The first-level instruction cache is a direct-mapped cache


with 4KBytes of data total and 8-byte blocks. The second-
level cache is a two-way set associative, write-back, write-
allocate cache with 2MBytes of data total and 32-Byte
blocks.
Contd:

The first-level instruction cache has a miss-rate of 2%. The


first-level data cache has a miss-rate of 15%. The unified
second-level cache has a local miss rate of 10% (i.e. the
miss rate for all accesses going to the second-level cache).
Assume that 40% of all instructions are data memory
accesses; 60% of those are loads, and 40% are stores.
Assume that 50% of the blocks in the second-level cache
are dirty at any time. Assume that there is no optimization for
fast reads on an L1 or L2 cache miss.
Contd.
All first-level cache hits cause no stalls. The second-level hit
time is 10 cycles (That means that the L1 miss-penalty,
assuming a hit in the L2 cache, is 10 cycles). Main memory
access time is 100 cycles to the first bus width of data; after
that, the memory system can deliver consecutive bus widths
of data on each following cycle. Outstanding, non-
consecutive memory requests can not overlap; an access to
one memory location must complete before an access to
another memory location can begin. There is a 128-bit bus
from memory to the L2 cache, and a 64-bit bus from both L1
caches to the L2 cache. Assume that the TLB never causes
any stalls.
Questions…
1. What fraction of all data memory references cause a main
memory access (main memory is accessed before the
memory request is satisfied)? First show the equation,
then the numeric result.

2. How many bits are used to index each of the caches ie


Instruction, Data and L2 ?

3. What is the average memory access time in cycles


(including instructions and data memory references)? First
show the equation, then the numeric result. Hint: don’t
forget to consider dirty lines in the L2 cache.
Our example
100 cycles Penalty
10 cycles Penalty

L1
I$ L2
4KB
Unified
Processor Main
L1
Cache
2MB Memory
D$
8KB

64 bit bus 128 bit bus


How to interpret data

L1 Data Cache L1 Instruction Cache L2 Unified Cache

Size 8 KB Size 4 KB Size 2MB


Block size 8 byte Block size 8 byte Block size 32 byte
Direct mapped Direct mapped Two way set-assoc.
Write through Miss rate = 2% Write back
Write allocate Write allocate
Miss rate = 15% Miss rate = 10%

60% of which are loads


40% of all instructions are
data memory accesses 40% of which are stores

Assume that 50% of the blocks in L2 are dirty at any time

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