15CS302J OPERATING SYSTEMS

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 UNIT I: INTRODUCTION
• Computer System Overview-Basic Elements, Basic Linux
commands
• Instruction Execution, Memory Hierarchy
• Interrupts, Cache Memory, Direct Memory Access
• Operating system overview-objectives and functions
• Evolution of Operating System.

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 Operating System

• Exploits the hardware resources of one or more

processors
• Provides a set of services to system users
• Manages secondary memory and I/O devices

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 Basic Elements

I/O
Processor Modules

Main System
Memory Bus
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 Processor

Controls the Performs the data

operation of the processing
computer functions

Referred to as the
Central Processing
Unit (CPU)
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 Main Memory
•Volatile
• Contents of the memory is lost
when the computer is shut down
•Referred to as real memory or
primary memory

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 I/O Modules

storage (e.g.
Moves data hard drive)
between the
computer and communications
external equipment
environments
such as:
terminals
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 System Bus

• Provides for communication

among processors, main
memory, and I/O modules

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 CPU Main Memory
0
System 1
2
PC MAR Bus
Instruction
Instruction
Instruction
IR MBR

I/O AR
Data
Execution
unit Data
I/O BR Data
Data

I/O Module n-2

n-1

PC = Program counter
Buffers IR = Instruction register
MAR = Memory address register
MBR = Memory buffer register
I/O AR = Input/output address register
I/O BR = Input/output buffer register

Figure 15CS302J
1.1 Computer
OPERATINGComponents: Top-Level
SYSTEMS LECTURE NOTES View
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 Microprocessor

• Invention that brought about desktop

and handheld computing
• Processor on a single chip
• Fastest general purpose processor
• Multiprocessors
• Each chip (socket) contains multiple
processors (cores)
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 Graphical Processing
Units (GPU’s)

• Provide efficient computation on arrays of

data using Single-Instruction Multiple Data
(SIMD) techniques
• Used for general numerical processing
• Physics simulations for games
• Computations on large spreadsheets
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 Digital Signal Processors
(DSPs)

• Deal with streaming signals such as audio

or video
• Used to be embedded in devices like
modems
• Encoding/decoding speech and video
(codecs)
• Support for encryption and security
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 System on a Chip
(SoC)

•To satisfy the requirements of handheld

devices, the microprocessor is giving way to
the SoC
•Components such as DSPs, GPUs, codecs
and main memory, in addition to the
CPUs and caches, are on the same
chip
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 Instruction Execution

•A program consists of a set of instructions

stored in memory

processor reads
processor executes
(fetches) instructions
each instruction
from memory

Two steps
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 Fetch Stage Execute Stage

Fetch Next Execute

START HALT
Instruction Instruction

Figure 1.2 Basic Instruction Cycle

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•The processor fetches the instruction from
memory
•Program counter (PC) holds address of the
instruction to be fetched next
PC is incremented after each fetch

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Instruction Register (IR)

Fetched instruction is • Processor interprets the

loaded into Instruction instruction and performs
Register (IR) required action:
• Processor-memory
• Processor-I/O
• Data processing
• Control

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15CS302J OPERATING SYSTEMS LECTURE NOTES
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 Fetch Stage Execute Stage
Memory CPU Registers Memory CPU Registers
300 1 9 4 0 3 0 0 PC 300 1 9 4 0 3 0 1 PC
301 5 9 4 1 AC 301 5 9 4 1 0 0 0 3 AC
302 2 9 4 1 1 9 4 0 IR 302 2 9 4 1 1 9 4 0 IR
• •
• •
940 0 0 0 3 940 0 0 0 3
941 0 0 0 2 941 0 0 0 2
Step 1 Step 2
Memory CPU Registers Memory CPU Registers
300 1 9 4 0 3 0 1 PC 300 1 9 4 0 3 0 2 PC
301 5 9 4 1 0 0 0 3 AC 301 5 9 4 1 0 0 0 5 AC
302 2 9 4 1 5 9 4 1 IR 302 2 9 4 1 5 9 4 1 IR
• •
• •
940 0 0 0 3 940 0 0 0 3 3+2=5
941 0 0 0 2 941 0 0 0 2
Step 3 Step 4
Memory CPU Registers Memory CPU Registers
300 1 9 4 0 3 0 2 PC 300 1 9 4 0 3 0 3 PC
301 5 9 4 1 0 0 0 5 AC 301 5 9 4 1 0 0 0 5 AC
302 2 9 4 1 2 9 4 1 IR 302 2 9 4 1 2 9 4 1 IR
• •
• •
940 0 0 0 3 940 0 0 0 3
941 0 0 0 2 941 0 0 0 5
Step 5 Step 6

Figure 1.4 Example of Program Execution

(contents of memory and registers in hexadecimal)
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 Interrupts

•Interrupt the normal sequencing of the processor

•Provided to improve processor utilization
• most I/O devices are slower than the processor
• processor must pause to wait for device
• wasteful use of the processor

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 Table 1.1 Classes of Interrupts

Program Generated by some condition that occurs as a result of an

instruction execution, such as arithmetic overflow, division by
zero, attempt to execute an illegal machine instruction, and reference
outside a user's allowed memory space.

Timer Generated by a timer within the processor. This allows the

operating system to perform certain functions on a regular
basis.

I/O Generated by an I/O controller, to signal normal

completion of an operation or to signal a variety of error
conditions.

Hardware Generated by a failure, such as power failure or memory

failure parity error.

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 User I/O User
Program Program Program

1 4 1

I/O
Command
WRITE WRITE
5
2a
END
2

2b

WRITE WRITE
Figure 1.5a
3a
Flow of Control
3
Without Interrupts
3b

WRITE WRITE

(a) No interrupts (b) Inter

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 User I/O User I/O User
Program Program Program Program Program

1 4 1 4 1

I/O I/O
Command Command
WRITE WRITE WRITE
5
2a
END

Figure 1.5b
2

Interrupt
2

2b Handler

WRITE WRITE 5 WRITE

Short I/O Wait 3a

END

3 3

3b

WRITE WRITE WRITE

(a) No interrupts (b) Interrupts; short I/O wait

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(c) In
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 I/O User I/O User I/O
Program Program Program Program Program

4 1 4 1 4

I/O I/O I/O

Command Command Command
WRITE WRITE
5
2a
Figure 1.5c
END
2

Interrupt Interrupt
2b Handler Handler

WRITE 5 WRITE 5
Long I/O Wait END END
3a

3b

WRITE WRITE

No interrupts (b) Interrupts; shortOPERATING

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(c) Interrupts; long I/O wait
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 User Program Interrupt Handler

i
Interrupt
occurs here i+1

Figure 1.615CS302J
Transfer of Control via Interrupts
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 Fetch Stage Execute Stage Interrupt Stage

Interrupts
Disabled
Check for
Fetch next Execute interrupt;
START instruction instruction initiate interrupt
Interrupts
handler
Enabled

HALT

Figure 1.7 Instruction Cycle with Interrupts

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Time

1 1

4 4
I/O operation
I/O operation;
processor waits 2a concurrent with
processor executing

5 5

2b
2
4
I/O operation
4 3a concurrent with
processor executing
I/O operation;
processor waits 5

5 3b

(b) With interrupts

3

(a) Without interrupts

Figure 1.8 Program Timing: Short I/O Wait

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Time

1 1

4 4

I/O operation; 2 I/O operation

processor waits concurrent with
processor executing;
then processor
waits
5

5
2
4
4
3 I/O operation
concurrent with
I/O operation; processor executing;
processor waits then processor
waits

5
5

3 (b) With interrupts

(a) Without interrupts

Figure 1.9 Program Timing: Long I/O Wait

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 Hardware Software

Device controller or
other system hardware
issues an interrupt
Save remainder of
process state
information
Processor finishes
execution of current
instruction

Process interrupt
Processor signals
acknowledgment
of interrupt
Restore process state
information
Processor pushes PSW
and PC onto control
stack
Restore old PSW
and PC
Processor loads new
PC value based on
interrupt

Figure
15CS302J1.10 Simple
OPERATING Interrupt
SYSTEMS Processing
LECTURE NOTES
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 T–M T–M
Y N+1
Control Control
Stack Stack
T T
N+1 Y+L+1
Program Program
Counter Counter

Y Start Y Start
Interrupt General Interrupt General
Service Registers Service Registers
Y + L Return Routine T Y + L Return Routine T–M
Stack Stack
Pointer Pointer

Processor Processor

T–M T

N User's N User's
N+1 N+1
Program Program

Main Main
Memory Memory

(a) Interrupt occurs after instruction

(b) Return from interrupt
at location N

Figure 1.11 Changes in Memory and Registers for an Interrupt

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 Multiple Interrupts

An interrupt occurs
while another interrupt Two approaches:
is being processed
• e.g. receiving data from • disable interrupts while
a communications line an interrupt is being
and printing results at processed
the same time • use a priority scheme

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 Interrupt
User Program Handler X

Interrupt
Handler Y

(a) Sequential interrupt processing

Interrupt
User Program Handler X

Interrupt
Handler Y

(b) Nested interrupt processing

Figure 1.12 Transfer

15CS302J of Control
OPERATING withLECTURE
SYSTEMS MultipleNOTES
Interrupts
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 Printer Communication
User Program
interrupt service routine interrupt service routine
t=0

15
0 t=
t =1

t = 25

t= t = 25 Disk
40 interrupt service routine

t=
35

Figure 1.13 Example Time Sequence of Multiple Interrupts

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 Memory Hierarchy

• Major constraints in memory

amount
speed
expense
• Memory must be able to keep up with the processor
• Cost of memory must be reasonable in relationship to
the other components

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 Memory Relationships

Greater capacity =
Faster access smaller cost per bit
time = greater
cost per bit Greater capacity =
slower access
speed

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 The Memory Hierarchy

Going down the g-

Re r s
e

hierarchy: Inb
Me oard
mo
i st

Ca
ch
e

in
ry M a or y
m
Me

decreasing cost per bit Ou Di

sk
t tic

increasing capacity Sto boar gne OM

rag d M a D- R W
e C D -R W
C R M
D-
D V D- R A y

increasing access time

a
DV lu-R
B

decreasing frequency of Of
S t o f - li n e ne
tic
Ta
p e

rag ag
access to the memory by e M

the processor

15CS302J OPERATING SYSTEMS LECTUREFigure

NOTES1.14 The Memory Hierarchy
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 T1 + T2

T2

Average access time

T1

0 1
Fraction of accesses involving only Level 1 (Hit ratio)

Figure 1.15 Performance of a Simple Two-Level Memory

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•Memory references by the processor tend to
cluster
•Data is organized so that the percentage of
accesses to each successively lower level is
substantially less than that of the level above
•Can be applied across more than two levels of
memory

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Secondary
Memory

Also referred to as
auxiliary memory
• external
• nonvolatile
• used to store program
and data files

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• Invisible to the OS
• Interacts with other memory management hardware
• Processor must access memory at least once per instruction cycle
• Processor execution is limited by memory cycle time
• Exploit the principle of locality with a small, fast memory

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 Block Transfer
Word Transfer

CPU Cache Main Memory

Fast Slow

(a) Single cache

Level 1 Level 2 Level 3 Main

CPU
(L1) cache (L2) cache (L3) cache Memory

Fastest Fast
Less Slow
fast

(b) Three-level cache organization

Figure 1.16 Cache and Main Memory

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Line Memory
Number Tag Block address
0 0
1 1
2 2 Block 0
3 (K words)

C-1
Block Length
(K Words)

(a) Cache

Block M – 1

2n - 1
Word
Length
(b) Main memory

Figure 1.17 Cache/Main-Memory Structure

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 START

RA - read address
Receive address
RA from CPU

Is block No Access main

containing RA memory for block
in cache? containing RA
Yes

Fetch RA word Allocate cache

and deliver slot for main
to CPU memory block

Load main
Deliver RA word
memory block
to CPU
into cache slot

DONE

Figure 1.18 Cache Read Operation

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 cache size

number of
cache block size
levels

Main
categories
are:

write mapping
policy function

replacement
algorithm

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 Cache and Block Size

Cache Size Block Size

the unit of data

small caches have
exchanged
significant impact
between cache
on performance
and main memory
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 Mapping Function

∗ Determines which cache

location the block will occupy
when one block is read in,
another may have to be
replaced
Two constraints affect
design:
the more flexible the
mapping function, the more
complex is the circuitry
required to search the cache
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Replacement Algorithm

 Least Recently Used (LRU) Algorithm

• effective strategy is to replace a block that has been
in the cache the longest with no references to it
• hardware mechanisms are needed to identify the
least recently used block

 chooses which block to replace when a new block is

to be loaded into the cache

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 Write Policy

Dictates when the memory write operation takes

place

• can occur every time the block is updated

• can occur when the block is replaced
• minimizes write operations
• leaves main memory in an obsolete state

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 I/O Techniques

∗ When the processor encounters an instruction relating to

I/O, it executes that instruction by issuing a command to the
appropriate I/O module

Three techniques are possible for I/O operations:

Programmed Interrupt- Direct Memory

I/O Driven I/O Access (DMA)

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 Programmed I/O

• The I/O module performs the requested action then

sets the appropriate bits in the I/O status register
• The processor periodically checks the status of the I/O
module until it determines the instruction is complete
• With programmed I/O the performance level of the
entire system is severely degraded

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 Interrupt-Driven I/O

Processor
issues an I/O The processor
command to a executes the
module and data transfer
then goes on and then
to do some resumes its
other useful former
work processing

The I/O module will More efficient than

then interrupt the Programmed I/O but still
processor to request requires active
service when it is intervention of the
ready to exchange processor to transfer
data with the data between memory
processor 15CS302J OPERATING SYSTEMS LECTURE NOTES
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 Interrupt-Driven I/O
Drawbacks

•Transfer rate is limited by the speed with which

the processor can test and service a device
•The processor is tied up in managing an I/O
transfer
 a number of instructions must be
executed for each I/O transfer

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 Direct Memory Access
(DMA)
∗ Performed by a separate module on the system bus or
incorporated into an I/O module

When the processor wishes to read or write data it issues a

command to the DMA module containing:
• whether a read or write is requested
• the address of the I/O device involved
• the starting location in memory to read/write
• the number of words to be read/written

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•Transfers the entire block of data directly to and
from memory without going through the
processor
• processor is involved only at the beginning and end of the
transfer
• processor executes more slowly during a transfer when
processor access to the bus is required
•More efficient than interrupt-driven or
programmed I/O
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 Symmetric Multiprocessors
(SMP)

• A stand-alone computer system with

the following characteristics:
• two or more similar processors of comparable capability
• processors share the same main memory and are
interconnected by a bus or other internal connection
scheme
• processors share access to I/O devices
• all processors can perform the same functions
• the system is controlled by an integrated operating system
that provides interaction between processors and their
programs at the job, task, file, and data element levels
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Performance Scaling
• a system with multiple • vendors can offer a range of
processors will yield greater products with different
performance if work can be price and performance
done in parallel characteristics

Availability Incremental Growth

• the failure of a single • an additional processor can
processor does not halt the be added to enhance
machine performance

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Processor Processor Processor
L1 Cache L1 Cache L1 Cache

L2 Cache L2 Cache L2 Cache

System Bus

Main I/O
Memory I/O Adapter
Subsystem

I/O
Adapter

I/O
Adapter

Figure 1.19 Symmetric Multiprocessor Organization

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 Multicore Computer

•Also known as a chip multiprocessor

•Combines two or more processors (cores) on a
single piece of silicon (die)
• each core consists of all of the components of an
independent processor
•In addition, multicore chips also include L2 cache
and in some cases L3 cache

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 Core 0 Core 1 Core 2 Core 3 Core 4 Core 5

32 kB 32 kB 32 kB 32 kB 32 kB 32 kB 32 kB 32 kB 32 kB 32 kB 32 kB 32 kB
L1-I L1-D L1-I L1-D L1-I L1-D L1-I L1-D L1-I L1-D L1-I L1-D

256 kB 256 kB 256 kB 256 kB 256 kB 256 kB

L2 Cache L2 Cache L2 Cache L2 Cache L2 Cache L2 Cache

12 MB
L3 Cache

DDR3 Memory QuickPath

Controllers Interconnect

3 8B @ 1.33 GT/s 4 20b @ 6.4 GT/s

Figure 1.20 Intel Core i7-990X Block Diagram

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Operating System

• A program that controls the execution of application

programs
• An interface between applications and hardware

Main objectives of an OS:

• convenience
• efficiency
• ability to evolve
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 Application programs
Application
programming interface
Application Libraries/utilities Software
binary interface
Operating system
Instruction Set
Architecture
Execution hardware

Memory
System interconnect
translation Hardware
(bus)

I/O devices
Main
and
memory
networking

Figure 2.1 Computer Hardware and Software Structure

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 Operating System Services

• Program development
• Program execution
• Access I/O devices
• Controlled access to files
• System access
• Error detection and response
• Accounting

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 Key Interfaces

•Instruction set architecture (ISA)

•Application binary interface (ABI)
•Application programming interface (API)

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 The Role of an OS

•A computer is a set of resources for the

movement, storage, and processing of
data
•The OS is responsible for managing these
resources

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 Operating System
as Software

•Functions in the same way as ordinary

computer software
•Program, or suite of programs, executed by
the processor
•Frequently relinquishes control and must
depend on the processor to allow it to regain
control

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 Computer System
I/O Devices
Memory
Operating I/O Controller Printers,
System keyboards,
Software digital camera,
I/O Controller etc.

Programs
and Data

I/O Controller

Processor Processor

Storage
OS
Programs

Data

Figure 2.2 15CS302J

The Operating System
OPERATING SYSTEMS as Resource
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Evolution of Operating Systems

A major OS will evolve over time for a

number of reasons:

hardware upgrades

new types of hardware

new services

Fixes

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 Evolution of
Operating Systems
 Stages include:

Time
Sharing
Multiprogrammed Systems
Batch Systems
Simple Batch
Systems
Serial
Processing
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Serial Processing

Earliest Computers: Problems:

• Scheduling:
• No operating system • most installations used a
• programmers interacted directly hardcopy sign-up sheet to
with the computer hardware reserve computer time
• Computers ran from a console • time allocations could run short
or long, resulting in wasted
with display lights, toggle computer time
switches, some form of input
• Setup time
device, and a printer
• a considerable amount of time
• Users have access to the was spent just on setting up the
computer in “series” program to run

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 Simple Batch Systems

• Early computers were very expensive

• important to maximize processor utilization
• Monitor
• user no longer has direct access to processor
• job is submitted to computer operator who batches
them together and places them on an input device
• program branches back to the monitor when finished

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 Monitor Point of View

Interrupt
Processing

• Monitor controls the sequence of Device

Drivers
events Monitor
Job
Sequencing
• Resident Monitor is software Control Language
always in memory Boundary
Interpreter

• Monitor reads in job and gives

control User
• Job returns control to monitor Program
Area

Figure 2.3 Memory Layout for a Resident Monitor

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Processor Point of View

• Processor executes instruction from the memory containing

the monitor
• Executes the instructions in the user program until it
encounters an ending or error condition
• “control is passed to a job” means processor is fetching and
executing instructions in a user program
• “control is returned to the monitor” means that the
processor is fetching and executing instructions from the
monitor program

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Job Control Language (JCL)

Special type of programming

language used to provide
instructions to the monitor

what compiler to use

what data to use

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 Desirable Hardware
Features
Memory protection for monitor

• while the user program is executing, it must not alter the memory area
containing the monitor

Timer

• prevents a job from monopolizing the system

Privileged instructions

• can only be executed by the monitor

Interrupts

• gives OS more flexibility in controlling user programs

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 Modes of Operation

User Mode Kernel Mode

• user program executes in • monitor executes in kernel
user mode mode
• certain areas of memory are • privileged instructions may
protected from user access be executed
• certain instructions may not • protected areas of memory
be executed may be accessed

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Simple Batch System Overhead

• Processor time alternates between execution of user

programs and execution of the monitor
• Sacrifices:
• some main memory is now given over to the monitor
• some processor time is consumed by the monitor
• Despite overhead, the simple batch system improves
utilization of the computer

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Multiprogrammed
Batch Systems

• Processor is
often idle
• even with
automatic job
sequencing
• I/O devices
are slow
compared to
processor

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 Uniprogramming

Program A Run Wait Run Wait

Time
(a) Uniprogramming

• The processor spends a certain amount of time

executing, until it reaches an I/O instruction; it
Program A Run mustWait
then wait untilRunthat I/O instruction
Wait
concludes before proceeding
Program B Wait Run Wait Run Wait
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Program A Run Wait Run Wait
Multiprogramming
Time
(a) Uniprogramming

Program A Run Wait Run Wait

Program B Wait Run Wait Run Wait

Run Run Run Run

Combined Wait Wait
A B A B
Time
(b) Multiprogramming with two programs

• There must be enough memory to hold the OS (resident monitor)

and one user program
Program A Run Wait Run Wait
• When one job needs to wait for I/O, the processor can switch to the
other job, which is likely not waiting for I/O
Program B Wait Run Wait Run
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 Program B Wait Run Wait Run Wait

Run Run Run Run

Combined
Multiprogramming
A B
Wait
A B
Wait

Time
(b) Multiprogramming with two programs

Program A Run Wait Run Wait

Program B Wait Run Wait Run Wait

Program C Wait Run Wait Run Wait

Run Run Run Run Run Run

Combined Wait Wait
A B C A B C
Time
(c) Multiprogramming with three programs

• Multiprogramming Figure 2.5 Multiprogramming Example

• also known as multitasking
• memory is expanded to hold three, four, or more
programs and switch among all of them
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 Multiprogramming Example

JOB1 JOB2 JOB3

Type of job Heavy compute Heavy I/O Heavy I/O
Duration 5 min 15 min 10 min
Memory required 50 M 100 M 75 M
Need disk? No No Yes
Need terminal? No Yes No
Need printer? No No Yes

Table 2.1 Sample Program Execution Attributes

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 Effects on Resource Utilization

Uniprogramming Multiprogramming
Processor use 20% 40%
Memory use 33% 67%
Disk use 33% 67%
Printer use 33% 67%
Elapsed time 30 min 15 min
Throughput 6 jobs/hr 12 jobs/hr
Mean response time 18 min 10 min

Table 2.2 Effects of Multiprogramming on Resource Utilization

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 100% 100%

CPU CPU
0% 0%
100% 100%

Memory Memory
0% 0%
100% 100%

Disk Disk
0% 0%
100% 100%

Terminal Terminal
0% 0%
100% 100%

Printer Printer
0% 0%

Job History Job History JOB1

JOB1 JOB2 JOB3
JOB2
0 5 10 15 20 25 30
minutes JOB3

0 5 10 15
time
minutes
time
(a) Uniprogramming (b) Multiprogramming

Figure 2.6 Utilization Histograms

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 Time-Sharing Systems

• Can be used to handle multiple interactive jobs

• Processor time is shared among multiple users
• Multiple users simultaneously access the system
through terminals, with the OS interleaving the
execution of each user program in a short burst or
quantum of computation

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 Batch Multiprogramming
vs. Time Sharing

Batch Multiprogramming Time Sharing

Principal objective Maximize processor use Minimize response time
Source of directives to Job control language Commands entered at the
operating system commands provided with the terminal
job

Table 2.3 Batch Multiprogramming versus Time Sharing

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 Compatible Time-Sharing Systems

CTSS
Time Slicing
• One of the first time-sharing • System clock generates interrupts at a
rate of approximately one every 0.2
operating systems seconds
• At each interrupt OS regained control
• Developed at MIT by a group known and could assign processor to another
as Project MAC user

• Ran on a computer with 32,000 • At regular time intervals the current

user would be preempted and
36-bit words of main memory, with another user loaded in
the resident monitor consuming
5000 of that • Old user programs and data were
written out to disk
• To simplify both the monitor and • Old user program code and data were
memory management a program restored in main memory when that
program was next given a turn
was always loaded to start at the
location of the 5000th word
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 0 0 0
Monitor Monitor Monitor
5000 5000 5000
JOB 3
10000
JOB 1
JOB 2
(JOB 2)
20000

Free 25000 25000

Free Free
32000 32000 32000
(a) (b) (c)

0 0 0
Monitor Monitor Monitor
5000 5000 5000
JOB 4
JOB 1
15000 JOB 2
(JOB 1)
20000 20000
(JOB 2) (JOB 2)
25000 25000 25000
Free Free Free
32000 32000 32000
(d) (e) (f)

Figure 2.7 CTSS Operation

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 Major Achievements

• Operating Systems are among the most complex

pieces of software ever developed

Major advances in
development include:
• processes
• memory management
• information protection and security
• scheduling and resource management
• system structure

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