A Nine Level Inverter Employing One DC Voltage Source and Reduced Components As High Frequency AC Power Supply
A Nine Level Inverter Employing One DC Voltage Source and Reduced Components As High Frequency AC Power Supply
INDUSTRIAL ELECTRONIC
ELECTRICALENGINEERING
DEPARTMENT
ME( PART III-IV)
Introduction
• With the increasing demands for power supplies in computer,
telecom, electric vehicle, and other similar areas where low
voltage and high current are needed, the traditional dc power
distribution system (DC PDS) is gradually unable to meet the
requirements due to its insufficiencies such as more conversion
stages, low efficiency and poor transient response.
1.5V 1 0 0 1 1 1 0 0 1
V 1 0 0 1 1 0 0 1 0
0.5V 1 0 0 1 0 0 0 1 1
0 0 1 0 1 0 0 0 1 1
-0.5V 0 1 1 0 0 0 0 1 1
-V 0 1 1 0 1 0 0 1 0
-1.5V 0 1 1 0 1 1 0 0 1
-2V 0 1 1 0 1 1 1 0 0
Mode-1 to 4
Mode 1 Mode 2
Mode 3 Mode 4
Waveform-1
Vop
TIME
WAVEFORMS OF VC1 & VC2
VC1
TIME
VC2
TIME
CAPACITORS CURRENT
WAVEFORM
IC1& IC2
TIME
Waveform Analysis
• Above slide fig shows The nine-level staircase output can be
synthesized by four quasi-square waves voi (i=1, 2, 3, 4),
whose amplitudes and conducting angles are ±Vdc/2 and i
correspondingly.
• The Fourier decomposition of each quasi-square is given by
below equation. where w is the angular frequency of the
staircase output.
• Third Harmonics Distortion Factor is given by below
equation
• THD = {(1/DF^2)-1}^0.5 ,where DF=Vs1/Vs
Capacitor calculation
• When the two capacitors in nine-level inverter discharge to
supply the load separately or in series with the voltage
source, voltage ripples will appear on them, which should
be limited to no more than 10% of the capacitors’ own
maximum voltage. so for this voltage ripple limitation, we
find minimum capacitance value by below formula.
Capacitance versus output frequency
with 10 Ω load
Current Waveform’s for different type
load
R=10
[5] 3 7 7 -
[6] 4 11 9 9
[7] 4 10 9 13
[8] 4 8 9 -
[9] 4 10 9 15
[10] 5 9 11 11
[11] 4 12 9 13
Advantages
• Compared with the existing topologies (hybrid , diode
clamped, capacitor clamped , symmetrical and asymmetrical
bridge topology), proposed topology can achieve multi-level
staircase output with only one voltage source, fewer power
devices and relatively less voltage stress.
• All these have enlarged its application scopes. Voltage
balance problem is avoided by the inherent self-voltage
balancing ability, which has simplified the modulation
circuits or algorithms, and the lower THD is realized without
using HFM methods.
• If we want to more improve then we use any PWM
techniques.
Application
• Hybrid electric vehicles. (uses dc and high frequency ac
source)
• Biomedical application of glow discharge.
• Inductive heating.(Brazing, Hardening, Melting)
Reference
• [1] J.-S. Choi and F.-S. Kang, “Seven-Level PWM Inverter
Employing Series-Connected Capacitors Paralleled to a Single
DC Voltage Source,” IEEE Trans. Ind. Electron., vol. 62, no. 6,
pp. 3448-3459, Jun. 2015.
• [2] E. Babaei and S. Laali, “Optimum Structures of Proposed
New Cascaded Multilevel Inverter With Reduced Number of
Components,” IEEE Trans. Ind. Electron., vol. 62, no. 11, pp.
6887-6895, Nov. 2015.
• [3] E. Babaei, S. Laali and Z. Bayat, “A Single-Phase Cascaded
Multilevel Inverter Based on a New Basic Unit With Reduced
Number of Power Switches,” IEEE Trans. Ind. Electron., vol.
62, no. 2, pp. 922-929, Feb.
• [4] Y. Ye, K. W. E. Cheng and J. Liu, “A Step-Up Switched-
Capacitor Multilevel Inverter With Self-Voltage Balancing,”
IEEE Trans. Ind. Electron., vol. 61, no. 12, pp. 6672-6680.
Dec. 2014
• [5] V. Thiyagarajan and P. Somasundaram, "Modified Seven
Level Symmetric Inverter with Reduced Switch Count",
Advances in Natural and Applied Sciences, Vol. 11, No. 7, pp.
264-271, 2017.
• [6] E. Babaei et al "A Single Phase Cascaded Multilevel
Inverter Based on a New Basic Unit With Reduced Number of
Power Switches" IEEE Tran. Ind. Electr., vol. 62,no . 2, pp922
-929, 2015.
• [7] E. Samadaei, Gholamian S. A., A. Sheikholeslami and J.
Adabi, "An Envelope Type (E-Type) Module: Asymmetric
Multilevel InvertersWith Reduced Components," IEEE Trans.
Ind. Elect., vol. 63, no. 11, pp. 7148-7156, 2016.
• [8] K. Ramani, M. A. Sathik, S Sivakumar, " A New
Symmetric Multilevel Inverter Topology Using Single and
Double Source Sub-Multilevel Inverters," Journal of Power
Elect., vol. 15, no. 1, pp. 96 -105, 2015
• [9] M. Jayabalan, B. Jeevarathinam and T. Sandirasegarane,
"Reduced switch count pulse width modulated multilevel
inverter," IET Power Electr., vol. 10, no. 1, pp. 10-17, 2017
• [10] R. R Karasani, V. B. Borghate, et al, “A Modified
Switched-Diode Topology for Cascaded Multilevel Inverters”,
Journal of Pow. Electr., vol. 16, no. 5, pp.1706 -1715, 2016.
• [11] E. Babaei, Laali S. and Alilu S., "Cascaded Multilevel
Inverter With Series Connection of Novel H-Bridge Basic
Units," IEEE Tran. Ind.Electr., vol. 61, no. 12, pp. 6664 -
6671, 2014
Thank You