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Serial Communication in Embedded Systems

The document discusses serial communication concepts including USART, RS232, baud rate, sampling rate, receivers, and transmitters. It provides details on configuring and using the serial port on an EB63 microcontroller for transmitting and receiving data using interrupts or polling. It includes an example Verilog module for a serial echo using asynchronous receivers and transmitters.

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Rishabh Ranjan
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© Attribution Non-Commercial (BY-NC)
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Download as PPT, PDF, TXT or read online on Scribd
105 views

Serial Communication in Embedded Systems

The document discusses serial communication concepts including USART, RS232, baud rate, sampling rate, receivers, and transmitters. It provides details on configuring and using the serial port on an EB63 microcontroller for transmitting and receiving data using interrupts or polling. It includes an example Verilog module for a serial echo using asynchronous receivers and transmitters.

Uploaded by

Rishabh Ranjan
Copyright
© Attribution Non-Commercial (BY-NC)
Available Formats
Download as PPT, PDF, TXT or read online on Scribd
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Serial Communication in

Embedded Systems
USART
• Universal
• Synchronous
• Asynchronous
• Receiver
• Transmitter
RS232
• RS232 is a long standing standard for
point to point serial communication.
• Transmission is carried out with voltage
levels between -5V and 5V or -12V and
12V.
Baud Rate
General Case
Baud = [Source Clock] / [Clock Divider]

EB63
Baud = [Source Clock] / (16 x [Clock Divider])
Sampling Rate
• In order to get reliable communication, the
USART must over sample the receive line.
• The higher the sampling rate the more
precise the USART can be.
• In general and in the case of the EB63, a
sampling rate of 16x the Baud Rate is
used.
Sampling Rate

Bit 1/0
Receiver
• The receiver must detect an incoming
transmission and then capture the data bits as
they arrive in the center of the Baud period.
• Each transmission includes one start and 1, 1.5
or 2 stop bits
• A start bit is the first part of the transmission and
the signal is low for one Baud period
• A stop bit is the last part of the transmission and
the signal is high for one to two Baud periods
after the last data bit.
Receiver

Sampling
clock

Baud
clock
Receiver
• The start bit is detected at the midpoint of
the baud period. Every baud period after
the start is detected the receiver captures
a data bit until all data bits are received.
This insures the bits are captured in the
center of the baud period.
Transmitter
• The transmitter uses the Baud Clock to
transition the serial signal to send data.
• In practice, the data is stored in a shift
register like logic. The transmitter first
sends the start bit followed each data bit
(MSB to LSB) shifting out of the shift
register. The transmission is ended with
the stop bits.
Transmitter

Held at 1 when idle


Always 0
Parity
• Due to noisy in the transmission lines,
errors can sometimes occur in the
transmission.
• To help correct this, parity bits may be
optional be included to detect error.
Parity Types
• Even Parity – Data Bits and Parity form a
even number of 1’s
• Odd Parity – Data Bits and Parity form a
odd number of 1’s
• Marked 1 – Parity forced high
• Marked 0 – Parity forced low
Data Size
• All transmissions have a start bit
• The eb63 RS232 port supports data sizes
of 5 through 9 bits of data per
transmission.
• Transmissions may have 1, 1.5 or 2 stop
bits.
Base USART Signals
• Rx – serial receive
• Tx – serial transmit
• GND – common ground
Modes of Operation
• Normal Operation – both Rx
and Tx are enabled.
• Automatic Echo – Tx is
disabled and Rx is looped
back to Tx.
• Local Loopback – Tx pin is
disabled and is looped back to
Rx.
• Remote Loopback – Rx is
disabled and the pin is looped
back to Tx.
EB63 USART
Baud Clock Generation
Control eb63 com port in Mmlite
step 1: clock control
1. Enable the clock in the power manager
ThePmc->PerClockEnable = ThePmc->PerClockStatus | PMCPC_USART1;
/* green part controls clock rate, black part packet size, no parity, 1 stop bit*/
2. Select the master clock
Usart1->Mode = USM_CLK_MCKI | USM_BPC_8 | USM_NONE | USM_1STOP;

3. Write clock divider to baud register


Usart1->Baud = 0x516; //1200 BAUD
/*25000000/(1302 x 16) = 1200.0768049155145929339477726575*/
Usart1->Baud = 0xA3; //9600 BAUD
/*25000000/(163 x 16) = 9585.8895705521472392638036809816*/
Step 2: Set up USART
1. Disable the PIO pins multiplexed with the USART
pins (st USART logic are exposed to the pins)
PioA->Disable = PIOA_TXD1 | PIOA_RXD1;
/*each symbol is the pin label (defined in the Mmlite header file) corresponding to the
PIO/USART pins) */
2. Set packet size, parity, stop bit size
Usart1->Mode = USM_CLK_MCKI | USM_BPC_8 | USM_NONE |
USM_1STOP ;
/* Select 8 data bits, no parity and 1 stop bit*/
3. Disable all interrupts
Usart1->IntrDisable = 0xffffffff;
/*This is a polling driver example, several other interrupts related to other
functions can be controlled in a similar fashion*/
4. Enable & reset the receiver and the transmitter and
reset status bits.
Usart1->Control = USC_RSTRX | USC_RSTTX | USC_RXEN | USC_TXEN |
USC_RSTSTA;
Polling Received Data
• Poll the RXRDY bit for the 32-bit receiver register (but
only 9 bits are used.)
rxrdy = Usart1->ChannelStatus & USI_RXRDY;
• Rxrdy is 1 after a packet is received. You can read the
contents of the register
val = Usart1->RxData;
• Rxrdy is reset after the receiver register is read.
• The content of the register is overwritten if it is not read
before the next packet is received, and the “overrun” bit
of the status register is flagged.
Transmitting Data
• Poll the transmitter until it is not busy in sending the
current packet
txrdy = Usart1->ChannelStatus & USI_TXRDY;
/* 0: Tx is busy, 1: Tx is ready to send next packet */
• If txrdy is not zero, write the packet (in 32-bit write
instruction) to the transmit holding register and the
transmission will begin
Usart1->TxData = val;
Using the MMlite Com Driver
• There exists an interrupt based serial driver
available for you to use already in MMlite.
• If you need to use your own serial port driver,
you must disable the existing driver and rebuild
the operating system. More details for that will
be provided later.
How to use the serial port driver in Mmlite
1. Opening the Com port
PIFILE OpenCom2(void)
{
PIFILE f;
SCODE sc =
BindToObject(CurrentNameSpace(), "com2", NAME_SPACE_READ, IID_IFile,
(void**) &f);
if (FAILED(sc)) {
printf("Could not open com2??\n");
return NULL;
}
Usart1->Baud = 0x516; //1200 BAUD
return f;
}

Mmlite driver uses a file pointer to point to the driver.


This function returns a file pointer to the read and write buffers of the com driver
2. Receiving Data
int ReadOneInteger(PIFILE f)
{
int n = 0;
UINT nbytes;
SCODE sc;

sc = f->ReadAt(UINT64_ZERO,(BYTE*)&n,(UINT)1,&nbytes);
if (FAILED(sc) || (nbytes == 0)) {
printf("Could not read from com2, sc=%x nb=%d\n",sc,nbytes);
return 0;
}

return n;
}

This function reads a single byte from the read buffer. Note: this is a blocking read. If the
buffer is empty when this is called it will not return until something comes into the
buffer for it to return.
3. Transmitting Data
int WriteOneInteger(PIFILE f, int n)
{
UINT nbytes;
SCODE sc;

sc = f->WriteAt(UINT64_ZERO,(BYTE*)&n,(UINT)1,&nbytes);
if (FAILED(sc)) {
printf("Could not write com\n");
return -1;
}
return 1;
}

This writes a single byte to the write buffer for transmission.


Example
c2 = OpenCom2();
val = ReadOneInteger(c2);
printf("Recieved %x\n",val);
WriteOneInteger(c2, val);
printf("Transmitted %x\n",val);

These functions may be used in your client program to


perform serial communication.
Serial in Verilog/FPGA
module serialecho(CLK,RX,TX);
input CLK, RX;
output TX;
This is a sample
wire rdysrt; module using a serial
wire [7:0] data;
receiver and
async_receiver ar( transmitter than
.clk(CLK),
.RxD(RX), performs an echo.
.RxD_data_ready(rdysrt),
.RxD_data(data)
//.RxD_endofpacket,
//.RxD_idle You may use these
);
modules to start but
async_transmitter at( you must modify them
.clk(CLK),
.TxD_start(rdysrt), to meet all
.TxD_data(data), requirements of your
.TxD(TX)
//.TxD_busy() lab assignment
);

endmodule
Receiver
CLK – Source Clock (T9 on
async_receiver ar( the Spartan III)
.clk(CLK), RxD – Receive Pin (T13 on
.RxD(RX), the Spartan III)
.RxD_data_ready(rdysrt), RxD_data_ready – data ready,
.RxD_data(data) pulses high when data is valid
//.RxD_endofpacket, RxD_endofpacket – asserts
after a period of time, used
//.RxD_idle
when receiving multiple
); sequential packets
RxD_idle – asserts after a time
out to signal nothing is being
received
Transmitter
CLK – Source Clock (T9
async_transmitter at(
on the Spartan III)
.clk(CLK),
.TxD_start(rdysrt), TxD – Transmit Pin (R13
.TxD_data(data), on the Spartan III)
.TxD(TX) TxD_start – start
//.TxD_busy() transmission, pulse this to
); begin sending data
TxD_busy – transmitter
busy, the transimitter is
already sending data

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