OR GATE

MODULE ORG(Y,A,B);
INPUT A,B;
OUTPUT Y;
OR A1(Y,A,B);
ENDMODULE
NOT GATE
MODULE NOTG(Y,X);
INPUT X;
OUTPUT Y;
NOT A2(Y,X);
ENDMODULE
NAND GATE
MODULE NANDG(Y,A,B);
INPUT A,B;
OUTPUT Y;
NAND A3(Y,A,B);
ENDMODULE
NORGATE
MODULE NORG(Y,A,B);
INPUT A,B;
OUTPUT Y;
NOR A4(Y,A,B);
ENDMODULE
HALF ADDER

MODULE HAG(S,C,A,B);
INPUT A,B;
OUTPUT S,C;
XOR X1(S,A,B);
AND X2(C,A,B);
ENDMODULE

FULL ADDER
MODULE FAG(S,C,A,B,CIN); W1
INPUT A,B,CIN;
OUTPUT S,C;
WIRE [3:1]W;
XOR X1(W[1],A,B);
AND X2(W[2],A,B);
XOR X3(S,W[1],CIN); W3
AND X4(W[3],CIN,W[1]);
OR X5(C,W[2],W[3]); W2
ENDMODULE
TEST BENCH OF HALFADDER
• TEST BENCH FULL ADDER
MODULE HAG_TB; MODULE FAG_TB;
REG A,B; REG A,B,CIN;
WIRE S,C;
WIRE S,C;
HAG H1(S,C,A,B);
INITIAL FAG H1(S,C,A,B,CIN);
REPEAT(100) INITIAL
BEGIN
REPEAT(100)
A=$RANDOM;
B=$RANDOM; BEGIN
#100; A=$RANDOM;
END
B=$RANDOM;
ENDMODULE
CIN=$RANDOM;
#100;
END
ENDMODULE
HALF SUBSTRACTOR
MODULE HSG(D,BOR,A,B);
INPUT A,B;
OUTPUT D,BOR;
WIRE W1;
XOR X1(D,A,B);
NOT X2(W1,A);
AND X3(BOR,W1,B);
ENDMODULE

FULL SUBSTRACTOR
MODULE FSG(D,BOR,A,B,BIN);
INPUT A,B,BIN;
OUTPUT D,BOR;
W1
WIRE [5:1]W;
XOR X1(W[1],A,B); W5
NOT X5(W[2],A); W2 W3
AND X2(W[4],W[2],B);
XOR X3(D,W[1],BIN);
NOT X6(W[3],W[1]); W4
AND X4(W[5],BIN,W[1]);
OR X5(BOR,W[4],W[5]);
ENDMODULE
TEST BENCH OF HALFADDER
• TEST BENCH FULL ADDER
MODULE HSG_TB; MODULE FSG_TB;
REG A,B; REG A,B,BIN;
WIRE S,C;
WIRE D,BOR;
HSG H1(D,BOR,A,B);
INITIAL FSG H1(D,BOR,A,B,BIN);
REPEAT(100) INITIAL
BEGIN
REPEAT(100)
A=$RANDOM;
B=$RANDOM; BEGIN
#100; A=$RANDOM;
END
B=$RANDOM;
ENDMODULE
BIN=$RANDOM;
#100;
END
ENDMODULE
MULTIPLEXER 2:1

MODULE MUX21(Y,I,S);
INPUT [1:0]I;
INPUT S;
OUTPUT Y;
WIRE [3:1]W; W3
NOT A1(W[1],S);
AND A2(W[2],I[0],W[1]);
AND A3(W[3],I[1],S);
OR A4(Y,W[2],W[3]); W1 W2
ENDMODULE
TEST BENCH OF HALFADDER
• TEST BENCH FULL ADDER
MODULE HAG_TB; MODULE FAG_TB;
REG A,B; REG A,B,CIN;
WIRE S,C;
WIRE S,C;
HAG H1(S,C,A,B);
INITIAL FAG H1(S,C,A,B,CIN);
REPEAT(100) INITIAL
BEGIN
REPEAT(100)
A=$RANDOM;
B=$RANDOM; BEGIN
#100; A=$RANDOM;
END
B=$RANDOM;
ENDMODULE
CIN=$RANDOM;
#100;
END
ENDMODULE
 MULTIPLEXER 4:1

MODULE MUX41(Y,I,S); W3
INPUT [3:0]I;
INPUT [1:0]S;
OUTPUT Y;
W4
WIRE [6:1]W;
NOT A1(W[1],S[0]);
NOT A2(W[2],S[1]);
W5
AND A3(W[3],I[0],W[1],W[2]);
AND A4(W[4],I[1],W[1],S[1]);
AND A5 (W[5],I[2],S[0],W[2]);
AND A6 (W[6],I[3],S[0],S[1]); W6
OR A7(Y,W[6],W[5],W[4],W[3]);
ENDMODULE W2

W1
DECODER 3:8
MODULE DEC38(D,A,B,C);
INPUT A,B,C;
OUTPUT [7:0]D;
WIRE [3:1]W;
NOT A1(W[1],A);
NOT A2(W[2],B);
NOT A3(W[3],C);
AND A4(D[0],W[1],W[2],W[3]);
AND A5(D[1],W[1],W[2],C);
AND A6(D[2],W[1],B,W[3]);
AND A7(D[3],W[1],B,C);
AND A8(D[4],A,W[2],W[3]);
AND A9(D[5],A,W[2],C);
AND A10(D[6],A,B,W[3]);
AND A11(D[7],A,B,C);
ENDMODULE
ENCODER 4:2
MODULE ENC42(X,Y,D2,D3,D1);
INPUT D2,D3,D1;
OUTPUT X,Y;
WIRE [3:1]W;
 Module Instances
Syntax

Port Order Connections

module_name instance_name [instance_array_range] (signal, signal, ... );
Port Name Connections
module_name instance_name [instance_array_range] (.port_name(signal), (.port_name(signal),
...);
 Module Instances
 A module may be instantiated using port order or port names.
• Port order instantiation lists signal connections in the same order as the
port list in the module definition. Unconnected ports are designated by
two commas with no signal listed.
• Port name instantiation lists the port name and signal connected to it, in
any order.
• instance_name (required) is used to make multiple instances of the same
module unique from one another.
• instance_array_range (optional) instantiates multiple modules, each
instance connected to separate bits of a vector.
Exor gate
MODULE XORG(Y,A,B);
INPUT A,B;
OUTPUT Y;
XOR X1(Y,A,B);
ENDMODULE
AND GATE
MODULE ANDG1(A,B,Y);
INPUT A,B;
OUTPUT Y;
AND X2(Y,A,B);
ENDMODULE
HALF ADDER
MODULE HAG(S,C,A,B);
INPUT A,B;
OUTPUT S,C;
XORG X3(S,A,B);
ANDG1 X4(A,B,C);
ENDMODULE
FULL ADDER
MODULE FAG(S,C,A,B,CIN);
INPUT A,B,CIN;
OUTPUT S,C;
WIRE [3:1]W;
XORG X1(W[1],A,B);
ANDG1 X2(A,B,W[2]);
XORG X3(S,W[1],CIN);
ANDG1 X4(CIN,W[1],W[3]);
OR X5(C,W[2],W[3]);
ENDMODULE

FULL ADDER USING 2 HALF ADDER’S ,OR GATE

MODULE FAG2(S,C,A,B,CIN);
INPUT A,B,CIN;
OUTPUT S,C;
WIRE [3:1]W;
HAG X1(W[1],W[2],A,B);
HAG X2(S,W[3],W[1],CIN); W1 W3
OR X3(C,W[2],W[3]);
ENDMODULE W2
PARALLEL ADDER
MODULE PAG(S,COUT,A,B,CIN);
INPUT [3:0]A,B;
INPUT CIN;
OUTPUT [3:0]S; C1 C0
C2
OUTPUT COUT;
WIRE [2:0]C;
FAG2 F1(S[3],COUT,A[3],B[3],C[2]);
FAG2 F2(S[2],C[2],A[2],B[2],C[1]);
FAG2 F3 (S[1],C[1],A[1],B[1],C[0]);
FAG2 F4(S[0],C[0],A[0],B[0[,CIN);
ENDMODULE
PARALLEL SUBSTRACTOR

X3 X2 X1
ADDER/SUBSTRACTOR
CARRY LOOK AHEAD GENERATOR
MULTIPLEXER 2:1

MODULE MUX2(Y,I,S);
INPUT [1:0]I;
INPUT S;
OUTPUT Y;
WIRE [3:1]W;
W3
NOT A1(W[1],S);
AND A2(W[2],I[0],W[1]);
AND A3(W[3],I[1],S);
OR A4(Y,W[2],W[3]); W2
ENDMODULE
W1
MULTIPLEXER 4:1 USING MUX2
MODULE MUX4(F,S,I); W1
INPUT [3:0]I;
INPUT [1:0]S; W2
OUTPUT F;
WIRE [2:1]W;
MUX2 M1(W[1],I[3:2],S[1]);
MUX2 M3(W[2],I[1:0],S[1]);
MUX2 M4(F,W[2:1],S[0]);
ENDMODULE
Multiplexer 4:1
Multiplexer 4:1
Test bench for4:1 mux
Test bench for mux4:1
Test Bench mux 4:1
4 bit parallel adder
Test bench 4 bit parallel adder
Test bench 4 bit parallel adder
GATE DELAYS
GATE DELAYS
GATE DELAYS
 DATA FLOW MODELLING
Continuous Assignments
• A continuous assignment is the most basic statement in dataflow modeling, used
to drive a value onto a net. This assignment replaces gates in the description of the
circuit and describes the circuit at a higher level of abstraction. The assignment
statement starts with the keyword assign.
// Continuous assign. out is a net. i1 and i2 are nets.
assign out = i1 & i2;
// Continuous assign for vector nets. addr is a 16-bit vector net
// addr1 and addr2 are 16-bit vector registers.
assign addr[15:0] = addr1_bits[15:0] ^ addr2_bits[15:0];
// Concatenation. Left-hand side is a concatenation of a scalar
// net and a vector net.
assign {c_out, sum[3:0]} = a[3:0] + b[3:0] + c_in;
 Implicit Continuous Assignment
Instead of declaring a net and then writing a continuous assignment on the
net, Verilog provides a shortcut by which a continuous assignment can be
placed on a net when it is declared. There can be only one implicit declaration
assignment per net because a net is declared only once.
//Regular continuous assignment
wire out;
assign out = in1 & in2;
//Same effect is achieved by an implicit continuous assignment
wire out = in1 & in2;
• Implicit Net Declaration
If a signal name is used to the left of the continuous assignment, an implicit
net declaration will be inferred for that signal name. If the net is connected to
a module port, the width of the inferred net is equal to the width of the
module port.
// Continuous assign. out is a net.
wire i1, i2;
assign out = i1 & i2;
 Delays in Data Flow Modelling
• Regular Assignment Delay
• Implicit Continuous Assignment Delay
• Net Declaration Delay

Regular Assignment Delay:-

• The first method is to assign a delay value in a continuous assignment statement.
The delay value is specified after the keyword assign. Any change in values of in1 or
in2 will result in a delay of 10 time units before recomputation of the expression
in1 & in2, and the result will be assigned to out.
assign #10 out = in1 & in2; // Delay in a continuous assign
Implicit Continuous Assignment Delay
• An equivalent method is to use an implicit continuous assignment to specify
both a delay and an assignment on the net.

//implicit continuous assignment delay

wire #10 out = in1 & in2;
//same as
wire out;
assign #10 out = in1 & in2;
The declaration above has the same effect as defining a wire out and declaring a
continuous assignment on out.
NET DECLARATION DELAY
OPERATORS
LOGICAL OPERATORS
RELATIONAL
EQUALITY OPERATORS
BIT WISE
REDUCTION
CONDITIONAL
 Program of Carry look ahead adder generator
module fulladd4(sum, c_out, a, b, c_in);
output [3:0] sum;
output c_out;
input [3:0] a,b;
input c_in;
wire p0,g0, p1,g1, p2,g2, p3,g3;
wire c4, c3, c2, c1;
assign p0 = a[0] ^ b[0],
p1 = a[1] ^ b[1],
p2 = a[2] ^ b[2],
p3 = a[3] ^ b[3];
assign g0 = a[0] & b[0],
g1 = a[1] & b[1],
g2 = a[2] & b[2],
g3 = a[3] & b[3];
assign c1 = g0 | (p0 & c_in),
c2 = g1 | (p1 & g0) | (p1 & p0 & c_in),
c3 = g2 | (p2 & g1) | (p2 & p1 & g0) | (p2 & p1 & p0 & c_in),
c4 = g3 | (p3 & g2) | (p3 & p2 & g1) | (p3 & p2 & p1 & g0) |(p3 & p2 & p1 & p0 & c_in);
assign sum[0] = p0 ^ c_in,
sum[1] = p1 ^ c1,
sum[2] = p2 ^ c2,
sum[3] = p3 ^ c3;
assign c_out = c4;
endmodule
 DECODER 2:4 USING SHIFT OPERATOR
module decoder2x4(out,in);
input [1:0] in;
output [3:0] out;
assign out=1'b1<<in;
endmodule

Mux 2:1 using conditional operator

module mux_2x1(a,b,y,s);
input a,b,s;
output y;
assign y=s?b:a;
endmodule
 Mux 8:1 using conditional operator
module mux_8x1(i0,i1,i2,i3,i4,i5,i6,i7,y,s);
input i0,i1,i2,i3,i4,i5,i6,i7;
input [2:0]s;
output y;
assign y=s[2]?(s[1]?(s[0]?i7:i6):(s[0]?i5:i4)):(s[1]?(s[0]?i3:i2):(s[0]?i1:i0));
endmodule
DECODER 2:4 using conditional operator
module dec_2x4(i0,i1,o0,o1,o2,o3);
input i0,i1;
output o0,o1,o2,o3;
assign o3=i1?(i0?1’b1:1’b0):1’b0;
assign o2=i1?(i0?1’b0:1’b1):1’b0;
assign o1=i1?(i0?1’b0:1’b0):(i0?1’b1:1’b0);
assign o0=i1?(i0?1’b0:1’b0):(i0?1’b0:1’b1);
endmodule
 Decoder 3:8 using conditional operator
module dec_3x8(i0,i1,i2,o0,o1,o2,o3,o4,o5,o6,o7);
Input i0,i1,i2;
output o0,o1,o2,o3,o4,o5,o6,o7;
assign o7=i2?(i1?(i0?1:0):0):0;
assign o6=i2?(i1?(i0?0:1):0):0;
assign o5=i2?(i1?0:(i0?1:0)):0;
assign o4=i2?(i1?0:(i0?0:1)):0;
assign o3=i2?0:(i1?(i0?1:0):0);
assign o2=i2?0:(i1?(i0?0:1):0);
assign o1=i2?0:(i1?0:(i0?1:0));
assign o0=i2?0:(i1?0:(i0?0:1));
endmodule
 Multiplier 4 bit using conditional operator
module mul_partpro(a,b,o);
input [3:0]a;
input [3:0]b;
output [7:0]o;
wire [7:0]o1;`
wire [7:0]o2;
wire [7:0]o3;
wire [7:0]o4;
assign o1=b[0]?({4'b0000,a[3:0]}):8'b00000000;
assign o2=b[1]?({3'b000,a[3:0],1'b0}):8'b00000000;
assign o3=b[2]?({2'b00,a[3:0],2'b00}):8'b00000000;
assign o4=b[3]?({1'b0,a[3:0],3'b000}):8'b00000000;
assign o=o1+o2+o3+o4;
endmodule
WAP using data flow
MODULE ORG(Y,A,B);
INPUT A,B;
OUTPUT Y;
OR A1(Y,A,B);
ENDMODULE
NOT GATE
MODULE NOTG(Y,X);
INPUT X;
OUTPUT Y;
NOT A2(Y,X);
ENDMODULE
NAND GATE
MODULE NANDG(Y,A,B);
INPUT A,B;
OUTPUT Y;
NAND A3(Y,A,B);
ENDMODULE
NORGATE
MODULE NORG(Y,A,B);
INPUT A,B;
OUTPUT Y;
NOR A4(Y,A,B);
ENDMODULE
HALF ADDER

MODULE HAG(S,C,A,B);
INPUT A,B;
OUTPUT S,C;
XOR X1(S,A,B);
AND X2(C,A,B);
ENDMODULE

FULL ADDER
MODULE FAG(S,C,A,B,CIN); W1
INPUT A,B,CIN;
OUTPUT S,C;
WIRE [3:1]W;
XOR X1(W[1],A,B);
AND X2(W[2],A,B);
XOR X3(S,W[1],CIN); W3
AND X4(W[3],CIN,W[1]);
OR X5(C,W[2],W[3]); W2
ENDMODULE
HALF SUBSTRACTOR
MODULE HSG(D,BOR,A,B);
INPUT A,B;
OUTPUT D,BOR;
WIRE W1;
XOR X1(D,A,B);
NOT X2(W1,A);
AND X3(BOR,W1,B);
ENDMODULE

FULL SUBSTRACTOR
MODULE FSG(D,BOR,A,B,BIN);
INPUT A,B,BIN;
OUTPUT D,BOR;
W1
WIRE [5:1]W;
XOR X1(W[1],A,B); W5
NOT X5(W[2],A); W2 W3
AND X2(W[4],W[2],B);
XOR X3(D,W[1],BIN);
NOT X6(W[3],W[1]); W4
AND X4(W[5],BIN,W[1]);
OR X5(BOR,W[4],W[5]);
ENDMODULE
MULTIPLEXER 2:1

MODULE MUX21(Y,I,S);
INPUT [1:0]I;
INPUT S;
OUTPUT Y;
WIRE [3:1]W; W3
NOT A1(W[1],S);
AND A2(W[2],I[0],W[1]);
AND A3(W[3],I[1],S);
OR A4(Y,W[2],W[3]); W1 W2
ENDMODULE
 MULTIPLEXER 4:1

MODULE MUX41(Y,I,S); W3
INPUT [3:0]I;
INPUT [1:0]S;
OUTPUT Y;
W4
WIRE [6:1]W;
NOT A1(W[1],S[0]);
NOT A2(W[2],S[1]);
W5
AND A3(W[3],I[0],W[1],W[2]);
AND A4(W[4],I[1],W[1],S[1]);
AND A5 (W[5],I[2],S[0],W[2]);
AND A6 (W[6],I[3],S[0],S[1]); W6
OR A7(Y,W[6],W[5],W[4],W[3]);
ENDMODULE W2

W1
DECODER 3:8
MODULE DEC38(D,A,B,C);
INPUT A,B,C;
OUTPUT [7:0]D;
WIRE [3:1]W;
NOT A1(W[1],A);
NOT A2(W[2],B);
NOT A3(W[3],C);
AND A4(D[0],W[1],W[2],W[3]);
AND A5(D[1],W[1],W[2],C);
AND A6(D[2],W[1],B,W[3]);
AND A7(D[3],W[1],B,C);
AND A8(D[4],A,W[2],W[3]);
AND A9(D[5],A,W[2],C);
AND A10(D[6],A,B,W[3]);
AND A11(D[7],A,B,C);
ENDMODULE
ENCODER 4:2
MODULE ENC42(X,Y,D2,D3,D1);
INPUT D2,D3,D1;
OUTPUT X,Y;
WIRE [3:1]W;
MULTIPLEXER 2:1

MODULE MUX2(Y,I,S);
INPUT [1:0]I;
INPUT S;
OUTPUT Y;
WIRE [3:1]W;
W3
NOT A1(W[1],S);
AND A2(W[2],I[0],W[1]);
AND A3(W[3],I[1],S);
OR A4(Y,W[2],W[3]); W2
ENDMODULE
W1
BEHAVIOUR MODELLING
INITIAL STATEMENT
ALWAYS STATEMENT
INTRA ASSGNMENT DELAY
EVENT BASED TIMING CONTROL
Use of @* Operator
CONDITIONAL STATEMENTS
 DFLIP FLOP

• module D_latch (Q,D,control);

• output Q;
• input D,control;
• reg Q;
• always @ (control or D)
• if (control) //Same as: if (control = 1)
• Q = D;
• else
• Q=0;
•
• endmodule
• module D_FF (Q,D,CLK);
• output Q;
• input D,CLK;
• reg Q;
• always @ (posedge CLK)
• Q = D;
• endmodule

• //D flip-flop with asynchronous reset.

• module DFF (Q,D,CLK,RST);
• output Q;
• input D,CLK,RST;
• reg Q;
• always @(posedge CLK or negedge RST)
• if (~RST) Q = 1'b0; // Same as: if (RST = 0)
• else Q = D;
• endmodule
• module TFF (Q,T,CLK,RST);
• output Q;
• input T,CLK,RST;
• wire DT;
• assign DT = Q ^ T ;
• //Instantiate the D flip-flop
• DFF TF1 (Q,DT,CLK,RST);
• endmodule
• //JK flip-flop from D flip-flop and gates
• module JKFF (Q,J,K,CLK,RST);
• output Q;
• input J,K,CLK,RST;
• wire JK;
• assign JK = (J & ~Q) | (~K & Q);
• DFF JK1 (Q,JK,CLK,RST);
• //D flip-flop
• module DFF (Q,D,CLK,RST);
• output Q;
• input D,CLK,RST;
• reg Q;
• always @ (posedge CLK or negedge RST)
• if (~RST) Q = 1'b0;
• else Q = D;
• endmodule
• module mux8x1if(i,s,o);
• input [7:0] i;
• input [2:0] s;
• output o;
• reg o;
• always @(i,s)
• if(s[2]==1)
• if(s[1]==1)
• if(s[0]==1)
• o=i[7];
• else
• o=i[6];
• else
• if(s[0]==1)
• o=i[5];
• else
• o=i[4];
• else
• if(s[1]==1)
• if(s[0]==1)
• o=i[3];
• else
• else
• if(s[0]==1)
• o=i[1];
• else
• o=i[0];

• endmodule
Traffic Signal Controller
`define TRUE 1'b1
`define FALSE 1'b0
`define Y2RDELAY 3 //Yellow to red delay
`define R2GDELAY 2 //Red to green delay
module sig_control (hwy, cntry, X, clock, clear);
output [1:0] hwy, cntry;
reg [1:0] hwy, cntry;
input X;
input clock, clear;
parameter RED = 2'd0,
YELLOW = 2'd1,
GREEN = 2'd2;
parameter S0 = 3'd0, //GREEN RED
S1 = 3'd1, //YELLOW RED
S2 = 3'd2, //RED RED
S3 = 3'd3, //RED GREEN
S4 = 3'd4; //RED YELLOW
reg [2:0] state;
reg [2:0] next_state;
always @(posedge clock)
if (clear)
state <= S0; //Controller starts in S0 state
else
state <= next_state; //State change
always @(state)
begin
hwy = GREEN; //Default Light Assignment for Highway
cntry = RED; //Default Light Assignment for Country light
case(state)
S0: ; // No change, use default
S1: hwy = YELLOW;
S2: hwy = RED;
S3: begin
hwy = RED;
cntry = GREEN;
end
S4: begin
hwy = RED;
cntry = `YELLOW;
end
endcase
end
always @(state or X)
begin
case (state)
S0: if(X)
next_state = S1;
else
next_state = S0;
S1: begin //delay some positive edges of clock
Repeat(`Y2RDELAY) @(posedge clock) ;
next_state = S2;
end
S2: begin //delay some positive edges of clock
repeat(`R2GDELAY) @(posedge clock);
next_state = S3;
end
S3: if(X)
next_state = S3;
else
next_state = S4;
S4: begin //delay some positive edges of clock
repeat(`Y2RDELAY) @(posedge clock) ;
next_state = S0;
end
default: next_state = S0;
endcase
end
endmodule
 Test bench for traffic light
module stimulus;
wire [1:0] MAIN_SIG, CNTRY_SIG;
reg CAR_ON_CNTRY_RD;
reg CLOCK, CLEAR;
sig_control SC(MAIN_SIG, CNTRY_SIG, CAR_ON_CNTRY_RD, CLOCK, CLEAR);
initial
$monitor($time, " Main Sig = %b Country Sig = %b Car_on_cntry = %b",
MAIN_SIG, CNTRY_SIG, CAR_ON_CNTRY_RD);
initial
begin
CLOCK = `FALSE;
forever #5 CLOCK = ~CLOCK;
End
initial
begin
CLEAR = `TRUE;
repeat (5) @(negedge CLOCK);
CLEAR = `FALSE;
End
initial
begin
CAR_ON_CNTRY_RD = `FALSE;
repeat(20)@(negedge CLOCK); CAR_ON_CNTRY_RD = `TRUE;
repeat(10)@(negedge CLOCK); CAR_ON_CNTRY_RD = `FALSE;
repeat(20)@(negedge CLOCK); CAR_ON_CNTRY_RD = `TRUE;
repeat(10)@(negedge CLOCK); CAR_ON_CNTRY_RD = `FALSE;
repeat(20)@(negedge CLOCK); CAR_ON_CNTRY_RD = `TRUE;
repeat(10)@(negedge CLOCK); CAR_ON_CNTRY_RD = `FALSE;
repeat(10)@(negedge CLOCK); $stop;
end
endmodule
• module mux81for(i,s,o);
• input [7:0] i;
• input [2:0] s;
• output o;
• reg o;
• integer k;
• always @(I or s)
• for(k=0;k<8;k=k+1)
• if(k==s)
• o=i[k];
• else
• o=1’b0;
• endmodule
module bcd2_seg(a,b,c,d,o1);
input a,b,c,d;
output [6:0]o1;
reg [6:0]o1;
always @ (a or b or c or d )
case({a,b,c,d})
4'b0000:o1=7'b1111110;
4'b0001:o1=7'b0110000;
4'b0010:o1=7'b1101101;
4'b0011:o1=7'b1111001;
4'b0100:o1=7'b0110011;
4'b0101:o1=7'b0011011;
4'b0110:o1=7'b0011111;
4'b0111:o1=7'b1110000;
4'b1000:o1=7'b1111111;
4'b1001:o1=7'b1110011;
4'b1010:o1=7'b1110111;
4'b1011:o1=7'b0011111;
4'b1100:o1=7'b1000011;
4'b1101:o1=7'b0111101;
4'b1110:o1=7'b0001111;
4'b1111:o1=7'b1001111;
default :o1=7'b0000000;
endcase
module bcd2_seg_tb();
reg a,b,c,d,lt,rbi;
reg bi;
wire [6:0]o1;
bcd2_seg x1(lt,rbi,bi,a,b,c,d,o1);
initial
begin
lt=1'b1;bi=1'b1;
# 150 lt=1'b0;
end
initial
begin
{rbi,a,b,c,d}=5'b10000;
# 10 {rbi,a,b,c,d}=5'bx0001;
# 10 {rbi,a,b,c,d}=5'bx0010;
# 10 {rbi,a,b,c,d}=5'bx0011;
# 10 {rbi,a,b,c,d}=5'bx0100;
# 10 {rbi,a,b,c,d}=5'bx0101;
# 10 {rbi,a,b,c,d}=5'bx0110;
# 10 {rbi,a,b,c,d}=5'bx0111;
# 10 {rbi,a,b,c,d}=5'bx1000;
# 10 {rbi,a,b,c,d}=5'bx1001;
# 10 {rbi,a,b,c,d}=5'bx1010;
# 10 {rbi,a,b,c,d}=5'bx1011;
# 10 {rbi,a,b,c,d}=5'bx1100;
# 10 {rbi,a,b,c,d}=5'bx1101;
# 10 {rbi,a,b,c,d}=5'bx1110;
# 10 {rbi,a,b,c,d}=5'bx1111;
# 10 {rbi,a,b,c,d}=5'bx1011; //for lt=0;
# 10 {rbi,a,b,c,d}=5'bx1100;
end
endmodule
module mag_id_comp(a,b,g1,g0,gre,eq,lt);
input [7:0]a,b;
input g1,g0;
output gre,eq,lt;
reg gre,eq,lt;
always @ (a or b or g1 or g0)
begin
if(g1==1'b0|g0==1'b0)
begin
if(a>b)
begin
gre=1'b1;
eq=1'b0;
lt=1'b0;
end
else if(a==b)
begin
gre=1'b0;
eq=1'b1;
lt=1'b0;
end
else
begin
gre=1'b0;
eq=1'b0;
lt=1'b1;
end
else
begin
gre=1'b1;
eq=1'b1;
lt=1'b1;
end

end
endmodule
 Test Bench for comparator
module mag_id_comp_tb();
reg [7:0]a,b;
reg g1,g0;
wire gre,eq;
integer i,j;
mag_id_comp x1(a,b,g1,g0,gre,eq);
initial
begin
repeat(3)
begin
for(i=0;i<=1;i=i+1)
begin
for(j=0;j<=1;j=j+1)
begin
g0=j;
g1=i;
# 10;
end
end
end
end
initial
fork
a=8'b10101010;
b=8'b01010101;
# 40 a=8'b01100110;
# 40 b=8'b01100110;
# 80 a=8'b00011110;
# 80 b=8'b01111000;
join

endmodule
BLOCK TYPES
 Nested blocks
//Nested blocks
initial
begin
x = 1'b0;
fork
#5 y = 1'b1;
#10 z = {x, y};
join
#20 w = {y, x};
end
 Generate Blocks
Generate statements are particularly convenient when the same
operation or module instance is repeated for multiple bits of a
vector, or when certain Verilog code is conditionally included
based on parameter definitions.

There are three methods to create generate statements:

• Generate loop
• Generate conditional
• Generate case
 Generate Loop
module bitwise_xor (out, i0, i1);
parameter N = 32; // 32-bit bus by default
output [N-1:0] out;
input [N-1:0] i0, i1;
genvar j;
generate for (j=0; j<N; j=j+1) begin: xor_loop
xor g1 (out[j], i0[j], i1[j]);
end
endgenerate
or
reg [N-1:0] out;
generate for (j=0; j<N; j=j+1) begin: bit
always @(i0[j] or i1[j]) out[j] = i0[j] ^ i1[j];
end
endgenerate
endmodule
module ripple_adder(co, sum, a0, a1, ci);
parameter N = 4; // 4-bit bus by default
output [N-1:0] sum;
output co;
input [N-1:0] a0, a1;
input ci;
wire [N:0] carry;
assign carry[0] = ci;
genvar i;
generate for (i=0; i<N; i=i+1) begin: r_loop
wire t1, t2, t3;
xor g1 (t1, a0[i], a1[i]);
xor g2 (sum[i], t1, carry[i]);
and g3 (t2, a0[i], a1[i]);
and g4 (t3, t1, carry[i]);
or g5 (carry[i+1], t2, t3);
end //end of the for loop inside the generate block
endgenerate //end of the generate block
assign co = carry[N];
endmodule
 Full adder using generate
module fulladder_gen(s,c,a,b,cin );
parameter N=10;
output [N-1:0] s,c;
input [N-1:0] a,b,cin;
genvar i;
generate for(i=0;i<N;i=i+1)
begin: fulladder_gen
xor x1(s[i],a[i],b[i],cin[i]);
assign c[i]= (a[i]&b[i]|b[i]&cin[i]|cin[i]&a[i]);
end
endgenerate
endmodule
 Mux using generate
module mux_gen(y,s,a,b );
parameter N=10;
output [N-1:0] y;
input [N-1:0]a,b;
input s;
genvar i;
generate for(i=0;i<N;i=i+1)
begin: mux_gen
assign y[i]=s?b[i]:a[i];
end
endgenerate
endmodule
 Barrel shifter
module bar_sft(a,s,lr,o);
input [7:0]a;
input lr;
input [2:0]s;
output [7:0]o;
reg [7:0]o;
always @ (s or lr or a)
begin
if(lr==1'b0)
begin
case(s)
3'b000:o=a;
3'b001:o=(a<<1);
3'b010:o=(a<<2);
3'b011:o=(a<<3);
3'b100:o=(a<<4);
 3'b101:o=(a<<5);
3'b110:o=(a<<6);
3'b111:o=(a<<7);
endcase
end
else
begin
case(s)
3'b000:o=a;
3'b001:o=(a>>1);
3'b010:o=(a>>2);
3'b011:o=(a>>3);
3'b100:o=(a>>4);
3'b101:o=(a>>5);
3'b110:o=(a>>6);
3'b111 :o=(a>>7);
endcase
end
end
endmodule
 Barrel shifter test
module bar_sft_tb();
reg [7:0]a;
reg [2:0]s;
reg lr;
wire [7:0]o;
bar_sft u1(a,s,lr,o);
initial
begin
s=3'b000;
# 25 s=3'b001;
# 25 s=3'b010;
# 25 s=3'b011;
# 25 s=3'b100;
# 25 s=3'b101;
# 25 s=3'b110;
# 25 s=3'b111;
# 25 s=3'b000;
# 25 s=3'b001;
# 25 s=3'b010;
# 25 s=3'b011;
# 25 s=3'b100;
# 25 s=3'b101;
# 25 s=3'b110;
# 25 s=3'b111;
# 25;
end
initial
begin
a=8'b11110011;
lr=1'b0;
# 200 lr=1'b1;
end

endmodule