CHAPTER 4:

(Additional Notes )
 Fetch & Execute Cycle
 Memory Interleaving
1. Fetch & Execute Cycle
 Machine Cycle

To/From MEMORY
FOUR Basic Operation:
4 1
STORE FETCH 1. FETCH – Obtain instruction from MEMORY
2. DECODE – Translate instruction into command
in CONTROL UNIT
3 2 3. EXECUTE – Execute instruction/command
EXECU DECOD in Arithmetic Logic Unit (ALU)

T
I
UN
TE E OL 4. STORE – Write result from (3) into
MEMORY
In

TR
A

N
LU

CO
In

Machine Cycle
Instruction Cycle
 In the Instruction Cycle, there are two-cycle operation in memory:
 Fetch (STEP 1 + STEP2 ) – Detail next slide

 Execute

 As previous, instruction in CPU will be hold by several registers such as:

A (accumulator) or GP(General Purpose): Hold data value between
instructions
 PC(program Counter): Determines next instruction for execution
 IR Instruction Register): Hold current instruction while it is being
executed
 MAR (Memory Address Register) & MDR (Memory Data Register):
Used for accessing memory
Every instruction MUST be fetched from
MEMORY
before it can be executed.
 Instruction Cycle – STEP 1

PC MAR
 Transfer value in PC (address of current
instruction) into MAR, so that computer
can retrieve in instruction located at the
address.
 As a result, instruction that located in MAR
will be transferred to MDR (in STEP 2)

** PC: Program counter, MAR: Memory Address Register

 Instruction Cycle – STEP 2

MDR IR
 Instruction in MDR will be transferred to
IR
 As a result, IR will hold the instruction
data until the next cycle or other task
took place.

** MDR: Memory Data Register , IR: Instruction Register

Process of Fetch/Execute Cycle

1. LOAD Fetch / Execute Cycle

2. STORE Fetch/Execute Cycle
3. ADD Fetch/Execute Cycle
LOAD Fetch / Execute Cycle

Process Description

1. PC -> MAR Transfer address from PC to the MAR

2. MDR -> IR Transfer instruction to the IR

3. IR(address)->MAR Address portion of the instruction loaded in MAR

4. MDR ->A Actual data copied into the accumulator (A)

5. PC+1 -> PC Program counter incremented

STORE Fetch / Execute Cycle

Process Description

1. PC -> MAR Transfer address from PC to the MAR

2. MDR -> IR Transfer instruction to the IR

3. IR(address)->MAR Address portion of the instruction loaded in MAR

4. A -> MDR* Accumulator copies data into MDR

5. PC+1 -> PC Program counter incremented

* Notice how Step 4 differs for LOAD and STORE

ADD Fetch / Execute Cycle

Process Description

1. PC -> MAR Transfer address from PC to the MAR

2. MDR -> IR Transfer instruction to the IR

3. IR(address)->MAR Address portion of the instruction loaded in MAR

4. A + MDR -> A Contents of MDR added to contents of accumulator

5. PC+1 -> PC Program counter incremented

You need to read slide no 4 – 11
to answer the following question.
Example 1
Question: Assume the following values are present just prior to execution of this segment:

Program Counter: 45
Value in Memory Location 44: 398 (ADD 98)
Value in Memory Location 45: 599 (LOAD 99)
Value in Memory Location 46: 123
Value in Memory Location 98: 777
Value in Memory Location 99: 210

At the end of each step in the instruction circle, give the contents of the following:
Answer: Instruction Answe Explanation (All answers /values from above)
r
1. PC -> MAR 45 (45) From value in program counter. Hence, we stated 45.
2. MDR -> IR 599 (599) From real value in memory location of 45 = 599
3. IR(address)->MAR 99 Value of 99 is taken from new address value assigned for 599 (LOAD
99)
4. MDR ->A 210 Actual data of new address (99) is copied to accumulator. Hence, we
stated 210.
5. PC+1 -> PC 46 PC incremented of existing value of PC.
Example 2

(2)

E R
S W
A N (1)

= Why 76? Because we retrieve from

previous operation.

(818)
We add value from previous accumulator
value, (1) =707 [ADDRESS IS 98] , with
new address (2) value 99 [value is 111].
Hence, we added both to get 818 in total.
2. Memory Interleaving
What is Memory Interleaving?

 Divide memory into parts - > Increase the effective rate of

memory access.
 Put in subsection with its own memory data register (MDR)
and memory address register (MAR)
 Possible to access more than 1 location at a time
Example 1
(From Jan2018 Final Exam)

Question. Illustrate a three-way memory interleaving from address 0

- 11
Answer:

0 1 2
MA MA MA
R 3 R 4 R 5
6 7 8
9 10 11

MD MD MD
R R R Address bus

data bus

2 3
1

* You need to draw memory interleaving with separate MAR and MDR as shown above.
Example 2

Question. Illustrate a four-way memory interleaving from address 0 -

11
Answer:

0 1 2 3
MA MA MA MA
R 4 R 5 R 6 R 7
8 9 10 11

MD MD MD MD
R R R R