Microprocessor

8086
Presented By

SUKANYA SAMANTA

©2017 Graphene Semiconductor Confidential

Index:

• Introduction

• Classification of microprocessor

• History of 8086

• Features

• Architecture of 8086

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Microprocessor

 Microprocessor is an integrated circuit which is also known as

the CPU of a computer to perform the core functions. It is the
brain of a computer.

 It accepts the binary data as input and performs the task and
produces the binary result.

 It is a silicon based chip which has 3 main units -

Arithmetic and logic Unit
Array Of Registers
Control Unit

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Block Diagram of a Computer

ALU

Input Control Unit Output

Device Device

Array of
Registers
Microprocessor

Memory

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Classification

 Based On Word length

• 8-bit - 8085
• 16-bit - 8086
• 32-bit - Pentiun pro processor
• 64-bit - Opteron

 Based On Architecture

• Complex Instruction Set Computing (CISC) - 8086

• Reduced Instruction Set Computing (RISC) - ARM

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RISC & CISC Architecture Comparison
CISC: Number of instruction is minimised with sacrificing number of cycles
to reduce the memory usage.

Machine Instruction
Instruction Execution

RISC: By using optimized set of instruction number of cycles per instruction is

reduced.This concept is used for portable devices.

Machine Microcode Microinstru- Microinstruction

Instruction Conversion ctions Execution

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History of 8086

Intel 8086 was launched in 1978.

It was the first 16-bit microprocessor.
This microprocessor has improved the execution speed of 8085 by
introducing pipeling architechture.
It is available in three versions:
8086 (5 MHz)
8086-2 (8 MHz)
8086-1 (10 MHz)
It consists of 29,000 transistors.

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Pipelining

Non-pipelined 8085

fetch1 execute1 fetch2 execute 2

Pipelined 8086

fetch1 execute1

fetch2 execute2

fetch3 execute3

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8086 Features
• 16-bit μp.
• 8086 has a 20 bit address bus which can access up to 2^20 memory
locations (1 MB).
• Can support up to 64K I/O ports.
• Provides 14, 16 -bit registers.
• Word length is 16 bit.
• It has multiplexed address and data bus AD0- AD15 and only address
bus A16 – A19.
• Requires single phase clock with 33% duty cycle to provide internal
timing.
• Can operate in two modes, Minimum and Maximum.
• It follows pipelined architecture.
• Requires +5V power supply.
• A 40 pin dual-in-line package.
• Address ranges from 00000H to FFFFFH

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8086 Architecture

http://www.eeeguide.com/8086-internal-architecture/

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•

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Internal Architecture 8086
The 8086 CPU logic has been partitioned into two functional units
namely Bus Interface Unit (BIU) and Execution Unit (EU).

Bus Interface Unit

• Fetching instructions
• Responsible for executing all external bus cycles.
• Read operands and write result.

Execution Unit
• Decodes instructions fetched by the BIU
• Generate control signals
• Executes instructions

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EU-General Purpose Registers

16-bit
8-bit 8-bit
AX AH AL Accumulator
BX BH BL Base
CX CH CL Count
DX DH DL Data
Pointer SP Stack Pointer
BP Base Pointer
SI Source Index
Index DI Destination Index

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General Purpose Registers

AX- Accumulator registor, stores the operands and result

BX- Base register, used to hold the starting/base address of memory in
data segment.
CX- Counter register, keeps the count of loop for loop instructions.
DX- Data register, used to hold the result.
SI - Source index register used as source in some satring processing
instructions for pointer addressing of data.
DI- Destination index register used as source in some satring processing
instructions for pointer addressing of data.
SP- Stack pointer is used to point the next instruction to be executed and
it is relative to stack segment.
BP- Base pointer is used in stack and ither segments to acces the data.

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EU-General Purpose Registers
SI - source index register:
Used as source in some satring processing instructions for pointer
addressing of data.

DI - destination index register:

Can be used for pointer addressing of data
Used as destination in some string processing instructions

BP - base pointer:
Primarily used to access parameters passed via the stack.

SP - stack pointer:
Always points to top item on the stack

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EU-Flag Registers
A flag is a flip flop which simply keeps the status of the execution as well as the
result . It is a 16-bit register(0-15) which consists of:
• 3 control flags
• 6 status flags.
• 7 undefined flags

U U U U OF DF IF TF SF ZF U AF U PF U CF

Undefined Direction Trap Zero Carry

Auxiliary Carry

Overflow Interrupt Sign Parity

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EU- Arithmetic Logic Unit

An arithmetic logic unit (ALU) represents the fundamental building block of the
central processing unit of a computer. An ALU is a digital circuit used to perform
arithmetic and logic operations.

A B

ALU

Result (Y)

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BIU-Instruction Byte Queue

It follows FIFO logic

After fetching the instructions in advance, it puts the instruction in
instruction byte queue upto 6 bytes
The BIU feeds the instruction stream to the execution unit through the 6
byte prefetch queue
The instruction byte queue is used to create the pipelined architecture in
terms of improving system speed.

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BIU-Segment Registers

CS(Code Segment) - Used to address the memory location which is in the

code segment of the memory.

DS(Data Segment) - Generally points at segment where variables are

defined.

ES(Extra Segment) - Extra segment register, it's up to a coder to define its

usage.

SS(Stack Segment) - points at the location containing in the stack segment

of the memory used for stack

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Memory Segments of 8086

segment register memory

code code

data data1

stack data2

extra stack

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BIU-Instruction Pointer & summing block

IP always points to next instruction to be executed

IP register always works together with CS segment register and it points to
currently executing instruction.
The value contained in the instruction pointer is called as an offset because this
value must be added to the base address of the code segment, which is available
in the CS register to find the 20-bit physical address.
Offset Value + Segment Register Value = Physical Address
15 0
Offset Address
19 5 0
Segment Register Value

Adder

20 bit Physical Address

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Example

If the data segment starts at location 1000h and a data reference contains
the address 29h where is the actual data?

Offset 0000 0000 0010 1001

Segment Address 0001 0000 0000 0000
Required Address 0001 0000 0000 0010 1001

*why segment address is needed to shift left by 4 bits?

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Segment and Address register combination

CS:IP
• SS:SP SS:BP
• DS:BX DS:SI
• DS:DI (for other than string operations)
• ES:DI (for string operations)

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Overview

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Thank You

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