Department of Computer Science and Engineering (CSE)

Unit 3
Intel 8086
MICROPROCESSOR

Prepared by:- Sanchit Mahajan

University Institute of Engineering (UIE)

 Department of Computer Science and Engineering (CSE)

OBJECTIVES
•To understand importance and applications of
microprocessors.
•To understand basic architecture of 8086 microprocessor.
•To understand the difference between MIN and MAX mode
operation.
•Interpret the timing diagrams of 8086.
•To understand the applications of 8086 microprocessor.

University Institute of Engineering (UIE)

 Department of Computer Science and Engineering (CSE)

OUTCOMES
• Students will understand each and every pin of 8086.
• Students will understand the basic block diagram of
8086.
• Students will get to know different type of instructions
that can be used for programming 8086.
• Students will understand the different modes of
addressing in 8086.

University Institute of Engineering (UIE)

 Department of Computer Science and Engineering (CSE)

INTRODUCTION
In 1978 , Intel released its first 16 bit microprocessor i.e.
8086 which executes the instructions at 2.5 MIPS(million /s)
[1]
• The execution time is 400 ns.
• An 8086 has 20 bit address bus, so it can access 2^20
=66Kb of memory.
• Width of the data bus of 8086 is 8 bit.

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 PIN DIAGRAM OF 8086

Figure: PIN DIAGRAM OF 8086 [1]

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 Department of Computer Science and Engineering (CSE)

Signals

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 Department of Computer Science and Engineering (CSE)

Internal Architecture of 8086 (cont..)

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 Department of Computer Science and Engineering (CSE)

Internal Architecture of 8086 (cont..)

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 Department of Computer Science and Engineering (CSE)

University Institute of Engineering (UIE)

 Department of Computer Science and Engineering (CSE)

Internal Architecture of 8086 (cont..)

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 Department of Computer Science and Engineering (CSE)

Minimum & Maximum Mode Interface

8086 Works in 2modes [2]:

1. Minimum : All control signals for memory and I/O are

generated by 8086. It is a uniprocessor configuration.
2. Maximum : Some control signals are generated externally
which requires the addition of external bus controller such
as 8288 to 8086. It is a multiprocessor configuration.

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 Department of Computer Science and Engineering (CSE)

Figure: Block Diagram of MIN mode OF 8086 [3]

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 Department of Computer Science and Engineering (CSE)

Figure: Block Diagram of MAX mode OF 8086 [3]

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 Department of Computer Science and Engineering (CSE)

University Institute of Engineering (UIE)

 Department of Computer Science and Engineering (CSE)

Various Pins of 8086

• Pins common to Minimum and Maximum modes:

» AD15-AD0
» A19/S6
» A18/S5
» A17/S4
» A16/S4
» BHE/S7
» RD
» READY
» INTR
» TEST
» CLK
» MN/MX

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 Department of Computer Science and Engineering (CSE)

Pins for the minimum mode operation

• M/IO
• INTA
• ALE
• DT/R
• DEN
• HOLD/HLDA

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 Department of Computer Science and Engineering (CSE)

Pins applicable for maximum mode operation of 8086

• S2, S1, S0
• LOCK
• QS1, QS0
QS1 QS0 Indication
0 0 No operation

0 1 First byte of the

opcode from the
queue
1 0 Empty queue
1 1 Subsequent byte
from the queue

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 Department of Computer Science and Engineering (CSE)

Architecture of 8086

It consists of two main section:

•EXECUTION UNIT- It consists of:

ALU
16 Bit General purpose registers- AX, BX, CX,
DX, SP, BP, SI , DI
16 BIT Flag registers
Control Unit

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 Department of Computer Science and Engineering (CSE)

• Bus Interface Unit : It consists of

• Adder for address calculations
• Four 16 bit segment registers
• A 16 bit Instruction pointer
• A 6 byte long instruction queue
• Control logic

 BIU and EU has been shown in the block diagram in the next
slide

19
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 Department of Computer Science and Engineering (CSE)

Figure: Internal block diagram of 8086 [4]

20
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 Department of Computer Science and Engineering (CSE)

Internal architecture of 8086

EU consists of eight 16 bit General Purpose Registers [5]

AX : Accumulator register is divided into AH and AL

BX: Base Register is divided into BH and BL
CX: Count Register is divided into CH and CL
DX: Data Register is divided into DH and Dl
SP: Stack Pointer
BP: Base Pointer
SI: Stack Index
DI: Destination Index

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 Department of Computer Science and Engineering (CSE)

OFFSET ADDRESS BASE ADDRESS

Stack Pointer Stack Segment

Base Pointer Stack Segment

Source Index Data Segment

Destination Index Extra Segment

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 Department of Computer Science and Engineering (CSE)

References
[1] Gaonkar, Ramesh S., “Microprocessor Architecture,
Programming & Applications with 8085”,Wiley Eastern Ltd.
[2] Ayala, “The 8086 Microprocessor: Programming & Interfacing
the PC” , Cengage Learning.
[3] Bhurchandi, K.M , Ray, A.K , “Advanced microprocessors and
peripherals”, TMH.
[4] Brey, “The Intel Microprocessors 8086- Pentium processor”, PHI.
[5] Triebel and Singh, Avtar , “The 8088 & 8086 Microprocessors-
Programming, interfacing, Hardware & Applications” , PHI .
[6] Liu,Yu-Chang & Gibson, Glenn A, “Microcomputer systems: The
8086/8088 Family: architecture, Programming & Design”, PHI.
[7] Antonakos, James L., “The Pentium processor”, Pearson
Education.

University Institute of Engineering (UIE)

 Department of Computer Science and Engineering (CSE)

FAQs

• Draw the structure of 8086 flag register and explain the

function of the flags with examples.
• How can we classify memory of 8086 in odd and even
memory bank. Explain in detail with diagram.
• Which interrupts are generally used for critical events?
• How can we classify memory of 8086 in odd and even
memory bank explain in detail with diagram.
• How flag register of 8086 is different from 8085? Which
flags are present in 8086 but not in 8085. Explain their
working.

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