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Microprocessor Is A Programmable Multipurpose Clock Driven Sequential Digital Integrated Electronic Component

The document discusses the 8085 microprocessor. It provides details on the architecture of the 8085 including its registers, address and data buses, instruction set, addressing modes, and interfacing with memory and I/O devices. It also covers interrupts and how they are handled by the 8085 microprocessor.

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47 views

Microprocessor Is A Programmable Multipurpose Clock Driven Sequential Digital Integrated Electronic Component

The document discusses the 8085 microprocessor. It provides details on the architecture of the 8085 including its registers, address and data buses, instruction set, addressing modes, and interfacing with memory and I/O devices. It also covers interrupts and how they are handled by the 8085 microprocessor.

Uploaded by

KUMARANSCR
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PPT, PDF, TXT or read online on Scribd
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Microprocessor and Microcontroller

Microprocessor is a
 Programmable

 Multipurpose

 Clock driven

 Sequential

 Digital

 Integrated electronic
component.
The Harvard architecture
The Von Neumann architecture
Evaluations of microprocessors

 HISTORY OF THE INTEL PROCESSORS


(1971-2019).mp4
PIN of 8085
8085 - SIGNALS

1. Address Bus
2. Data Bus.
3. Control & status signals
4. Power supply & frequency signals
5. Externally initiated signals
6. Serial I/O ports
The 8085 Bus Structure

The 8-bit 8085 Microprocessor communicates


with the other units using a 16-bit address bus,
an 8-bit data bus and a control bus.
The 8085 Bus Structure
Data Bus
 Consists of 8 data lines: D0 – D7
 Operates in bidirectional mode: The data bits are
sent from the MPU to peripheral devices, as well
as from the peripheral devices to the MPU.

 Data range: 00 (hex) – FF (hex)

Control Bus
 Consists of various lines carrying the control
signals such as read / write.
The 8085 Bus Structure

Address Bus
 Consists of 16 address lines: A0 – A15

 Operates in unidirectional mode: The address


bits are always sent from the MPU to peripheral
devices, not reverse.

 16 address lines are capable of addressing a


total of 216 = 65,536 (64k) memory locations.

 Address locations: 0000 (hex) – FFFF (hex)


8085 Functional Block Diagram
De multiplexing of Address and Data Bus
The 8085 CPU is Capable of
performing the following
 Store 8-bit data (Registers, Accumulator)
 Perform arithmetic and logic operations (ALU)

 Test for conditions (IF / THEN)

 Sequence the execution of instructions


 Store temporary data in RAM during execution
The 8085: CPU Internal Structure
The 8085: Registers
The 8085: CPU Internal Structure
Registers
 Six general purpose 8-bit registers: B, C, D, E, H, L

 They can also be combined as register pairs to


perform 16-bit operations: BC, DE, HL
 Registers are programmable (data load, move, etc.)
Accumulator
 Single 8-bit register that is part of the ALU !
 Used for arithmetic / logic operations – the result is
always stored in the accumulator.
Flag Bits
 Indicate the result of condition tests.

 Carry, Zero, Sign, Parity, etc.

 Conditional operations (IF / THEN) are executed


based on the condition of these flag bits.
Program Counter (PC)
 Contains the memory address (16 bits) of the
instruction that will be executed in the next step.
Example: Instruction Fetch Operation
Example: Instruction Fetch Operation
Memory Interfacing

 Select the chip (Address Decoding)


 Identify the register (Find the no. of
address lines required)
 Enable the appropriate buffer
Address Decoding Techniques

To identify the particular memory


location for the given address
Two types
 Absolute decoding / Full Decoding
 Partial Decoding /Linear decoding
Memory Interfacing

 Absolute decoding
A Memory location is identified by a
single address value
 Partial decoding
A Memory location is identified by
multiple address value
Interfacing the 16kb with 8085

2n =16000
log2n =log16000
n=log16000/log2
n=13.96(must be an integer)
n=14
Interfacing the 16kb with 8085
Interfacing the 16kb with 8085

Memory ICs A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 Address

Starting address of RAM 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 4000H

End address of RAM 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 7FFFH


Interfacing of three 16kB with 8085
Interfacing 32Kb EPROM and 32Kb RAM with 8085
I/O Interfacing

Two Types
 Memory mapped I/O

 I/O mapped I/O


Comparison between memory
mapped i/o &i/o mapped i/o

S.N Memory mapped I/O I/O mapped I/O


o
1 In this device address is 16 bit. In this device address is 8 bit. Thus A0 –
A0-A15 lines are used to A7 or A8-A15 lines are used to
generate device address. generate device address.
2 MEMR,MEMW control signals are IOR, IOW control signals are used to
used to control read &write I/O control read &write I/O operations.
operations.
3 Data transfer is between any Data transfer is between Accumulator
register and I/O device. and I/O device.
4 Maximum number of I/O devices Maximum number of I/O devices are
are 65536. 256.
5. Decoding 16 bit address may Decoding 16 bit address may require
require more hardware. less hardware.
6. LDA addr, STA addr IN port, OUT port
Interrupt
Interrupts

 Classification of Interrupts
 Interrupts can be classified into two types:
 Maskable Interrupts (Can be delayed or Rejected)
 Non-Maskable Interrupts (Can not be delayed or
Rejected)

 Interrupts can also be classified into:


 Vectored (the address of the service routine is hard-wired)
 Non-vectored (the address of the service routine needs to
be supplied externally by the device)
8085 Interrupts

TRAP
RST7.5
RST6.5
RST 5.5 8085
INTR
INTA
Interrupts

 Hardware Interrupts
Interrupt Vector address
1. TRAP 0024H
2. RST 7.5 003CH
3. RST 6.5 0034H
4. RST 5.5 002CH
Interrupts
 Software Interrupts
Interrupt Vector address
RST 0 0008
RST 1 0010
RST 3 0018
RST 4 0020
RST 5 0028
RST 6 0030
RST 7 0038
Addressing Mode

 Direct Addressing
 Indirect Addressing
 Register Addressing
 Immediate Addressing
 Implied Addressing
Instruction Set

 Data Transfer group


 Arithmetic Group
 Logical Group
 Branch Group
 Stack I/O, and Machine Control
Instructions
Data Transfer group

 MOV Move
 MVI Move Immediate
 LDA Load Accumulator Directly from Memory
 STA Store Accumulator Directly in Memory
 LHLD Load H & L Registers Directly from
 Memory
 SHLD Store H & L Registers Directly in Memory
 An 'X' in the name of a data transfer instruction implies that it
deals with a register pair (16-bits);
 LXI Load Register Pair with Immediate data
 LDAX Load Accumulator from Address in Register Pair
 STAX Store Accumulator in Address in Register Pair
 XCHG Exchange H & L with D & E
 XTHL Exchange Top of Stack with H & L
Arithmetic Group

 ADD Add to Accumulator


 ADI Add Immediate Data to Accumulator
 ADC Add to Accumulator Using Carry Flag
 ACI Add Immediate data to Accumulator Using Carry
 SUB Subtract from Accumulator
 SUI Subtract Immediate Data from Accumulator
 SBB Subtract from Accumulator Using Borrow (Carry) Flag
 SBI Subtract Immediate from Accumulator Using Borrow (Carry)
Flag
 INR Increment Specified Byte by One
 DCR Decrement Specified Byte by One
 INX Increment Register Pair by One
 DCX Decrement Register Pair by One
 DAD Double Register Add; Add Content of Register Pair to H & L
Register Pair
Logical Group
 ANA Logical AND with Accumulator
 ANI Logical AND with Accumulator Using Immediate Data
 ORA Logical OR with Accumulator
 OR Logical OR with Accumulator Using Immediate Data
 XRA Exclusive Logical OR with Accumulator
 XRI Exclusive OR Using Immediate Data
 CMP Compare
 CPI Compare Using Immediate Data
 RLC Rotate Accumulator Left
 RRC Rotate Accumulator Right
 RAL Rotate Left Through Carry
 RAR Rotate Right Through Carry
 CMA Complement Accumulator
 CMC Complement Carry Flag
 STC Set Carry Flag
Branch Group

 JMP Jump
 CALLCall
 RET Return
 Jumps Calls
 JC (Carry)
 JNC (No Carry)
 JZ (Zero)
 JNZ (Not Zero)
 JP (Plus)
 JM (Minus)
 JPE (Parity Even)
 JP0 (Parity Odd)
 PCHL Move H & L to Program Counter
 RST Special Restart Instruction Used with Interrupts
Stack I/O, and Machine Control
Instructions

 PUSH Push Two bytes of Data onto the Stack


 POP Pop Two Bytes of Data off the Stack
 XTHL Exchange Top of Stack with H & L
 SPHL Move content of H & L to Stack Pointer
 IN Initiate Input Operation
 OUT Initiate Output Operation
 EI Enable Interrupt System
 DI Disable Interrupt System
 HLT Halt
 NOP No Operation

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