Introduction to the digital flow in mixed

environment (2 - Back End)

Ecole de microélectronique 2017 IN2P3 [email protected]

Introduction

2
 Motivations

Give a start up methodology for digital back end flow for

• Implementation of digital blocks for small logic core (~ 50 k instances)
• Mixed Signal ASICs with a Digital on Top (DoT) / Mixed Signal (MS) flow
context

 Open Access (OA) based design

Timing Constraint design

3
 Back End Digital Flow
Technology Files Functional netlist
(liberty, qrc techfile, abstract, ...) Timing Constraints (sdc)
(.v, .vhd, .sv)

Synthesis (Genus) Formal Verification

(LEC)
Timing netlist (.v) map on std cells
not met and IP
Place and Route Signoff Verification
(Innovus) •DRC and LVS checking
(PVS)
• STA (Timing Check)
with Tempus
• Layout in OA / gds
• Netlist in Verilog
• Sdf file for post extraction
simulations
4
Prerequisites for
Back End Digital Flow
1. Interoperable PDK 4. Liberty files
2. Functional netlist 5. Timing Constraint
3. Abstract View 6. MMMC view

5
 1.Interoperable PDK

The Design Kit could be used in the

Virtuoso flow or in the Digital flow
• Common OA techfile
• Common qrc techfile for the
extraction

=> a common cds.lib for digital tools

and analog tools

6
 2.Synthesizable functional netlist

• For the same register, use only rising edge OR falling edge, not both

• Test Bench coding style is forbidden

• No reference for reading or writing in a text file
• No display message
• Assertion, probing or specific tools simulator commands (nc_mirror, …) are
banned

• You can not delay a signal from xxx ns; only clock cycle could be use to
synchronize your signals in your design.
i_ck80 <= NOT i_ck80 AFTER 6.25 ns

7
3. Abstract view in OA format for Std Cells / IP

These abstracts could be :

• provided by the foundry or the IP provider

• generated by the user with the virtuoso abstract generator

• generated from the lef files provided by the foundry

oa2lef –lef my_IP.lef –lib my_IP_OA_library

8
 4. Liberty Files

Foreach cell of a library, these files describe:

• The ports (input and output, power)
• The type of cells : buffer, inverter, and gate, io pads , …
• The operating condition
• The power consumption (optional)
• The timing modelling

These Liberty files are given by the foundry or could be generated for
custom IP with LIBERATE tool (see Xavier Liopart talk in 2015)

9
 5. Timing constraints (Sdc files )

• The sdc files (Synopsis Design Constraints) describe all the timing
information between your design and the outside:
• what are the clocks signals? What are the relation between clocks ?
• what is the delay between the signals and the clock?
• What is the input or output capacitance load ?
• What are the timing exceptions ?
• …..

• By default, the time unit is the ns

10
 6. Multi-Mode Multi-Corner view

• Multi Mode :
The chip have different functional modes (different clock speed, enable bit configuration, …)
=> One or more constraint modes associated with sdc files for each mode

• Multi Corner
There is different library set (process corner typical, slow, fast, …) and RC corners for timing
analysis (propagation delay, SI analysis)
=> Each delay corners combine liberty (.lib) for the std cells and QRC techfiles for the nets

=> MMMC view file combines constraint modes and delay corners to define
different scenarios (“Analysis View”)
• These analysis views are used for setup analysis and the hold during STA

11
 MMMC view: example
create_library_set -name tlf_typical -timing liberty/tsl18fs120_tt_1p8v_25c.lib -si Celtic/cells_tt_1p8v_25c.cdB
create_library_set -name tlf_max -timing liberty/tsl18fs120_ss_1p62v_125c.lib -si Celtic/cells_ss_1p62v_125c.cdB
create_library_set -name tlf_min -timing liberty/tsl18fs120_ff_1p98v_m40c.lib -si Celtic/cells_ff_1p98v_m40c.cdB

create_rc_corner -name Corner_RC_QRC -T 25 -qx_tech_file RCE_TS18SL_QRC_6M1L/qrcTechFile

create_delay_corner -name corner_ocv -rc_corner Corner_RC_QRC -early_library_set tlf_min -late_library_set tlf_max \

-early_opcond_library tsl18fs120_ff_1p98v_m40c -late_opcond_library tsl18fs120_ss_1p62v_125c \
-early_opcond ff_1p98v_m40c -late_opcond ss_1p62v_125c

create_constraint_mode -name mode_no_latch -sdc_files sdc/constraint_no_latch.sdc

create_constraint_mode -name mode_with_latch -sdc_files sdc/constraint_with_latch.sdc

create_analysis_view -name ocv_no_latch -constraint_mode mode_no_latch -delay_corner corner_ocv

create_analysis_view -name ocv_with_latch -constraint_mode mode_with_latch -delay_corner corner_ocv

set_analysis_view -setup [list ocv_no_latch ocv_with_latch] -hold [list ocv_no_latch ocv_with_latch]

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SDC files
1. Setup / Hold 4. Outputs
2. Clock 5. Timing exceptions
3. Inputs

13
 1. Setup and Hold checks (1/2)

The setup and hold timing checks are needed for proper propagation
of data through the sequential cells. These checks verify that the data
input is stable at the active clock edge.

• Setup time = minimum time with data stable before clock edge

• Hold time = minimum time with data stable after clock edge

14
Setup and Hold checks (2/2)

15
 Warnings !

The sdc files guide the digital tools during synthesis, placement and
routing to avoid setup or hold failure.
So be careful when you write them !

All path should be constrained to enable their analysis.

=> Unconstrained path can lead to “hidden” timing
violations or “over design”

16
 2. Clock: declaration

• Creating a clock
• create_clock command defines an ideal clock signal and specifies the ports or
pin that are connected to the clock.

• Example : definition of a clock :

• on port CLK
• with a 25ns period
• rising edge at 5 ns and falling edge at 12
create_clock [get_port CLK] -name m_clk -period 25 -waveform {5 12}

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 Clock: transition

• Clock Transition (slew)

• set_clock_transition 0.38 –rise clock_name

• set_clock_transition 0.38 –fall clock_name

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 Clock: uncertainty (skew)

Use the clock uncertainty to add margin for

setup/hold check or take in account clock jitter
and clock tree skew

• set_clock_uncertainty –setup 0.65 [get_clocks m_clk]

• set_clock_uncertainty –hold 0.65 [get_clocks m_clk]

19
 3. Input: declaration

• Input delay
• The input delay describes the arrival time on a port relative to the clock. It
could be for example the time needed for the data to go through
combinational logic before the module
• Use the –max argument for setup and –min for hold

create_clock -period 15 -waveform {5 12} [get_ports CLKP]

set_input_delay -clock CLKP -max 6.7 [get_ports INPA]
set_input_delay -clock CLKP -min 3.0 [get_ports INPA]

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Input: constraint

Max and min delays on input port.

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 4. Output: declaration

• Output delay :
Use the set_output_delay command to set the output path delay value for the
design

create_clock -period 20 -waveform {0 15} [get_ports CLKQ]

set_output_delay -clock CLKQ -min -0.2 [get_ports OUTC]
set_output_delay -clock CLKQ -max 7.4 [get_ports OUTC]

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Output : constraint

Max and min delays on output port.

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 Output: load

Use the set_load command to define the output load (in pF)
set_load -max 0.500 [all_outputs]
set_load -min 0.250 [all_outputs]

Tips:
To select all the inputs  all_inputs
To select all outputs  all_outputs

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 5. Timing exception

• False path:
When the designer wants to exclude a path (like reset) from the timing
analysis
set_false_path -from [get_ports rstb]

• Case analysis
When a signal is fixed to a logic value (configuration register, enable for scan
chain, …)
set_case_analysis 0 enable_latch

25
Synthesis
(Genus)
1. Library Setup 5. syn_map and syn_opt
2. Load Design / Elaborate 6. Write outputs
3. Constraints setup
4. syn_gen

26
 Synthesis flow (Genus)
GENUS
Functional netlists 1.Library Setup
(.v, .vhd, .sv)
2.Load Design / Elaborate
Verilog netlist mapped
3.Constraint Setup on std cells and IP
Technology Files
(liberty, qrc techfile)
4.Synthesizing to generic

5.Synthesizing to gates LEC scripts for Formal

and optimize the netlist verification
Timing Constraints (sdc)

6.Write Outputs
INNOVUS

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 Genus

• To launch genus :
linux:/> genus -legacy_ui
• Genus could be launched in batch mode with a .tcl script
genus –legacy_ui –files my_script.tcl

• By default, the GUI is not visible

legacy_genus:/> gui_show
legacy_genus:/> gui_hide

• To generate a template for synthesis flow

legacy_genus:/> write_template -outfile my_tempate.tcl

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 1. Synthesis: Library Setup

## setup the lib file

set_attribute init_lib_search_path { my_PDK_path/Std_cells/liberty}
set_attribute library {tsl18fs120_tt_1p8v_25c.lib}

## Provide the qrc_tech_file

set_attribute qrc_tech_file {my_PDK_path/QRC/qrcTechFile}

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 2. Synthesis : Load Design / Elaborate

# Load the design (Verilog, system Verilog or Vhdl files)

read_hdl –sv PE_valid_region.sv Respect a bottom up hierarchy
read_hdl –vhd reg_cmd.vhd when reading the design!
read_hdl main.v

## elaborate : Create a unique Verilog netlist for the design

elaborate main

## Verify undefined or black box module

check_design -unresolved

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 3. Synthesis: Constraint Setup

legacy_genus:/> read_sdc top_cell.sdc

Must have no
errors

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 4. Synthesis : syn_generic

## Synthesizing to generic
syn_generic

Design is map on custom

genus cells

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 Synthesis : check sdc constraints

## check if all the ports are constraints

report timing -lint

Every warning have to

be check

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 5. Synthesis: syn_map and syn_opt

### map generic netlist to cell from the library

syn_map

### optimize the netlist ( timing, power and area )

syn_opt

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 Synthesis: Timing report

• After each step

(syn_generic, syn_map,
syn_opt), do a timing
report

• report timing
Slack = timing margin
If slack <0 ?
 Redo an optimization
 Review your sdc file
 Review your functional netlist

35
 Synthesis: QOR
legacy_genus:/> report qor ===========================================
Generated by: Genus(TM) Synthesis Solution 16.13-s036_1
Generated on: Apr 12 2017 05:47:02 pm
Module: main
Before saving your design, do a Technology libraries: tsl18fs120_tt_1p8v_25c 1
physical_cells
Operating conditions: _nominal_
qor(Quality Of Result) report : Interconnect mode: global
Area mode: physical library
============================================================
 Gives information about Timing
--------

timing, area, instances used, … Cost Critical

Mode
Violating
Group Path Slack TNS Paths
-------------------------------------------------
main_clk 1072.6 0.0
-------------------------------------------------
Total 0.0 0

report qor > my_qor.txt Instance Count

--------------
Leaf Instance Count 3148
Sequential Instance Count 1068
Combinational Instance Count 2080
Hierarchical Instance Count 18

Area
----
Cell Area 124386.304
Physical Cell Area 0.000
Total Cell Area (Cell+Physical) 124386.304
Net Area 44730.429
Total Area (Cell+Physical+Net) 169116.733

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 6. Synthesis: Write Outputs

## write final netlist

write_hdl > main_m.v

### write final sdc

write_sdc > main_m.sdc

### write lec files

write_do_lec -revised_design main_m.v > rtl2final.lec.do

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 Synthesis: Summary
Set target library
set_attribute {library
name}
Read QRC techfile Synthesize
(optional) syn_generic
syn_map
syn_opt
Read HDL files
read_hdl {RTL netlist}

Elaborate the design Analyse and Report

elaborate

Apply optimization
directives

Write hdl and

Timing Met ? Innovus
outputs files

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Place and Route (P&R)
(Innovus)
1. Design Import 5. Check Timing
2. PreCTS 6. Save Design
3. CTS
4. NanoRoute and PostRoute

39
 P&R Flow

Synthesis
Innovus
Gate level netlist in 1.Design Import
verilog
Layout (OA or gds)
Technology Files 2.PreCTS Flow
+ netlist in verilog
( QRC techfile)
3.CTS Flow
OA libs defined by a
cds.lib 4.PostCTS Flow
Signoff Verification
MMMC View 5.Timing Checks STA (Tempus)
Definition File
6.Design Export DRC/LVS (PVS)

Power Analysis (Voltus)

40
 Innovus: start

• vdi licence option

Same tools, but :
• limited to 50k Instances.
• MMMC not available with this license  use Tempus license to run MMMC
• more licenses available at IN2P3.
linux:/> innovus -lic_startup vdi

• To start full version

linux:/> innovus
linux:/> innovus –log my_log -overwrite

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 Innovus: GUI
Menus Design Views :
• FloorPlan
Tools • AMOEBA
• Physical

Layer
control Bar

Name of the Cursor

selected object Coordinates
Design Status
42
 Innovus: Scripting vs GUI

• GUI :
 easy way to discover the commands and the tool
 more interactivity with the tools
 some commands are not accessible with the GUI

• Scripting (.tcl)
 not so easy to start writing a tcl script at the beginning
 script could be executed in background
 full option commands
 script could be easily reused

Tips : Every cmd (Graphical and scripted) are automatically transcripted in

the innovus .cmd file

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 1. Design Import
GUI Menus: Synthesize netlist

File /Import Design

Top cell name

OA reference libs:
Techfile first, then others Power/Ground nets
library

To import your design with tcl

commands : MMMC View
source XXX.globals
init_design

To save/load your
configuration in a .globals
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MMMC: Browser

45
 P&R: Some tools setup before PreCTS

• Specify the process node (180 nm, 90n, …) to tune your parasitic
extraction
• setDesignMode -process 180
• Specify the number of processor to use
• setMultiCpuUsage -localCpu 8
• Check for missing or inconsistent library and design datacheck
• checkDesign –all

46
 2. PreCTS: floorplaning

GUI Menus:
Floorplan /Specify Floorplan

47
 PreCTS: Pins placement

• GUI Menus:
Edit / Pin Editor

Warnings !
• Put your pins on the routing grid
• Avoid putting pin too close from
stripes
• Respect metal layer direction
• Even layer are vertical
• Odd layer are horizontal

48
 PreCTS: IP/Block placement

• Tcl command to place Macro Block and IP

placeInstance <instance_name> <location> <orientation>

Example :
placeInstance reg_row 50 12 R270

• With the GUI, select your instance and move it with your mouse.

49
 PreCTS: Power planning

1. Defines your stripes/rings

 GUI Menus:
Power / Power Planning
You can add
• Stripes (Horizontal or Vertical
power lines)
• Rings (around core or Blocks)

2. When your power planning is

finished, route your powers nets
with sroute command.

50
PreCTS: layout before cells placement

pins
Stripes
rows

51
 PreCTS: std cells placement

• New placer (GigaPlace) with Innovus

• GigaPlace place your std cells and do a first routing before the Clock
Tree Synthesis (CTS).

• The router (trialRoute) is not DRC signOff, but it is quick and give you
a good idea of the feasibility of your design (timing + congestion)

52
 PreCTS: Placement and optimization

1. Specify the top and bottom layer used for routing

• setRouteMode -earlyGlobalMaxRouteLayer 4
• setRouteMode -earlyGlobalMinRouteLayer 1

2. Place your std cells

• place_opt_design
3. Optimize your design if necessary
• optDesign -preCTS

53
place_opt_design vs placeDesign

54
Layout after placement

55
 3. CTS Flow

• Clock Trees are

• mandatory for synchronous design: one buffer can not drive every flip flop
• the clock should arrived almost at the same time at each flip flop => minimize
the Clock skew

Clock Tree Synthesis step (CTS) is done with CCOPT tool inside
innovus
ccopt_design (-cts)

56
 ccopt_design or ccopt_design -cts ?

• ccopt_design - cts
• with vdi licence
• need and optimization after
• ccopt_design
• with full innovus license

57
 CTS flow

1. Create a clock tree specification according to your sdc

create_ccopt_clock_tree_spec –filename ccopt.spec
source ccopt.spec
2. Run CCOpt or CCOpt-CTS
ccopt_design
3. Report timing and optimize if necessary (slack <0)
timeDesign – postCTS
optDesign -postCTS
timeDesign – postCTS –hold
optDesign –postCTS -hold

58
 CTS flow

4. Report on clock trees.

• report_ccopt_clock_trees –filename clock_trees.rpt
• report_ccopt_skew_groups –filename skew_groups.rpt

5. Open the CCOpt Clock Tree Debugger (CTD) Window.

ctd_win

Alternatively, use the “CCOpt Clock Tree Debugger” entry in the main GUI menu
(Clock menu)

59
 CTD window

clock
trees

clock
skew

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 Post CTS layout

Remarks : the routing is done with trialRoute = > some drc errors
are possible after routing
61
 4. PostCTS flow: NanoRoute

NanoRoute is a timing driven router. It’s also take in account :

• Crosstalk and Signal Integrity
• DRC / LVS issue
• process antenna violation
• nets and via optimization (add multi cut for example)

62
 Setting for NanoRoute

• Specify your Top and Bottom layer for routing

• setNanoRouteMode -routeTopRoutingLayer 4
• setNanoRouteMode -routeBottomRoutingLayer 1

• Turn on SI-driven routing

• setsignoffOptMode -fixGlitch true | false
• setNanoRouteMode -routeWithSiDriven true

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 Setting for NanoRoute

• Specify antenna fixing option

• setNanoRouteMode -drouteFixAntenna true
• setNanoRouteMode -routeAntennaCellName « my_diode »
• setNanoRouteMode -routeInsertAntennaDiode true

• When you have setup NanoRoute, route your design

Tcl command : routeDesign

64
 NanoRoute GUI

Diode Cell
name

Routing
options Min and max
Routing layer

65
 PostRoute: Verify the routing

• after each routing, check :

• the connectivity (open, short)
• verifyConnectivity
• DRC rules (metal spacing, cells overlap, …) Does not
• verifyGeometry replace DRC and
• process antenna LVS !!!
• verifyProcessAntenna

• You can see the result of your checks :

• in the Violation Browser
• in your console
• on your layout (errors are marked with white cross)

66
PostRoute: Violation browser

67
 PostRoute: Fixing routing errors

• Most of the time, redoing a routeDesign is enough

• If some errors remains, try to :
• Add or increase the strength of the cells
• Add diodes
• Delete path or nets with errors and re-routes them
• Move your std cells to avoid DRC errors spacing

• Tips : use “editDelete –net” to remove a routed net

editDelete -net PE_region/Imux_region/FE_RN_6_0
routeDesign

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 PostRoute: Optimization

Post Route optimization flow :

setExtractRCMode -engine postRoute Tools setup
setExtractRCMode -effortLevel signoff

timeDesign -postRoute
optDesign -postRoute -setup Timing
analyzing and
timeDesign -hold -postRoute
optimization
optDesign -postRoute -hold

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 PostRoute: Add Filler cells

When your
design has
no violation,
add filler
cells

addFiller -cell feedth feedth3 feedth9 -prefix FILLER

# do an eco route to fix DRC issue after Filler insertion
ecoRoute -fix_drc

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 5. Signoff Timing check with Innovus

Tcl commands :
timeDesign –signoff
timeDesign –signoff -hold

GUI menu :
Timing/Report Timing

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 Timing Debugging

GUI menu :
Timing/Debug Timing

TCL Script:
report_timing -machine_readable >top.mtarpt
load_timing_debug_report top.mtarpt

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 6. Save Design (1/2)

When timing checks (+ DRC, connectivity, …) are fine,

• Save the design in OA view
• saveDesign -cellview {libname cellname viewname}

• Export the final netlist

• saveNetlist main_EDI.v

Your design is mapped on abstract view ! Remaster

abstract views to layout view if needed in virtuoso
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 Save Design (2/2)

• Create an abstract of your block (in case of Digital On Top flow)

• save_abstract -lib lib_name -view abstract

• Export sdf for simulation

• write_sdf -view <analysis view name> my_sdf_file.sdf

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Summary of Innovus flow

75
Digital On Top (DoT) flow
1. AoT vs DoT
2. DoT Flow
 1. Analog On Top vs Digital On Top

• Analog On Top (AOT)

• Top level of the design is described with schematic
• Timing between analog and digital block is not critical
=> The design is assembled with virtuoso (layout XL flow)

• Digital On Top (DOT)

• Top level of the design is described with a netlist (in verilog if possible)
• Timing between blocks is critical
• Mixed Signal blocks are placed as black boxes
=> The design is assembled with Innovus

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 2. DOT flow

1. Digital routed and analog blocks are taken as abstract

• Analog Block must be Layout XL compliant, have a Boundary and if possible an
abstract
• To evaluate correctly the P-Cells, set this variable in your linux shell :
> setenv CDS_ENABLE_EXP_PCELL TRUE

2. You need an sdc file for the top module (and each submodule)
3. You have to provide the OA library (and if possible the .lib) of your macro
block

78
 DoT: Bottom up vs Top Down

• Bottom Up flow :
• You already have abstracts for your submodule and they are routed
independently from the top

• Top Down flow

• You have to define your partition (submodules) and the timing budget assign
to each partition. Innovus creates library for each components. You route
them later

79
 Place and route flow for Dot

Same classical flow as a standard block for placement and routing of

the top. Just consider macro block as “super std cells”
1. Import design
2. Place your macro bloc (IP or other submodules)
3. Route your powers and place your pins
4. Place std cells (if needed)
5. CTS (if needed)
6. NanoRoute
7. Save your design
8. exit

80
 DoT: Example of rooted top module design

Routed
Abstract for
nets
submodules

81
 DoT: Design Assembling for STA

Assembling your design allows innovus to “flatten” the abstracts of

submodule into smaller and smaller basic bricks (like std cells or IP)

1. Restart innovus
2. Before loading your design, make every block unique
> set init_design_uniquify 1
3. Restore your Design
> restoreDesign -cellview {lib_name cell_name view_name}

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 DoT: Design Assembling for STA

4. Assemble each module you want to flatten

assembleDesign -block {my_OA_lib my_celll my_view}

• Respect a top down hierarchy for the assembling

• This view is only for timing analysis. Do not use it later for routing!

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DoT: Example of a partially assembled design

Abstract for
unassembled
modules

Abstract for
unassembled
“Assembled” modules
module

84
 DoT: Design Assembling for STA

5. Save your design

saveDesign -cellview {lib_name cell_name view_name}

This view is only for STA ! Do not use it for LVS !

6. Perform STA with Innovus or Tempus on the whole chip

 timeDesign or report_timing commands

85
Conclusion

86
 Synthesis and P&R Flow
GENUS Innovus
Technology Files 1.Library Setup
(liberty, qrc techfile, 1.Design Import
abstract) 2.Load Design / Elaborate
2.PreCTS Flow • Layout in OA / gds
Functional netlist • Netlist in Verilog
3.Constraint Setup
(.v, .vhd, .sv) 3.CTS Flow • Sdf file for post
extraction simulations
4.Synthesizing to generic
4.PostCTS Flow
Timing Constraints 5.Synthesizing to gates
(sdc) 5.Timing Checks
and optimize the netlist

6.Write Outputs 6.Save Design

87
 DoT flow

• AoT vs DoT :
• AoT based on a schematic Virtuoso flow
• DoT based on a netlist  Innovus flow

• DoT and Mixed Signal P&R:

• Same flow as a full Digital flow; just considers blocks as “special std cells” or IP
• Do assembleDesign for STA checking
• For analog block, need a timing modeling (.lib) if the block interact with pure
digital modules

88
 For further informations on Digital Flow:

• About sdc :
“Static Timing Analysis for Nanometer Designs : a Practical Approach”
from J . Bhasker and Rakesh Chadha

• About Genus and Innovus tools

• Cadence Support website
• Cadence Rapid Adoption Kit (RAK)
• Cadence Training
• Genus, Innovus User Guide

89