COMPUTER SYSTEM

ORGANIZATION

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UNIT-I COMPUTER BASICS AND CPU:

 Von Newmann model

 Various subsystems

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 CPU, Memory, I/O, System Bus
 CPU and Memory registers
 Program Counter, Accumulator, Instruction
register,
 Micro operations, Register Transfer Language,
Instruction Fetch, decode and execution,
 Data movement and manipulation, Instruction
formats and addressing modes of basic
computer. 2
THE VON NEUMANN
ARCHITECTURE
DESIGNING COMPUTERS

 All computers more or less based on the same basic

design, the Von Neumann Architecture!

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 The basic concept behind the von Neumann
architecture is the ability to store program
instructions in memory along with the data on

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which those instructions operate.

 Until von Neumann proposed this possibility,

each computing machine was designed and built
for a single predetermined purpose.

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 THE VON NEUMANN ARCHITECTURE
Bus

Processor (CPU)

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Memory Input-Output
Control Unit

ALU
Communicate with
Store data and program
"outside world", e.g.
• Screen
Execute program
• Keyboard
Do arithmetic/logic operations • Storage devices 6
requested by program
 THE VON NEUMANN ARCHITECTURE
 Model for designing and building computers, based
on the following characteristics:
1) The computer consists of four main sub-systems:
Memory

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

 ALU (Arithmetic/Logic Unit)

 Control Unit
 Input/Output System (I/O)
2) Program and data both stored in same memory.
3) Program instructions are executed sequentially.

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THE CPU
 The CPU, which can be considered the heart of
the computing system, includes three main
components:

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 Control unit (CU)
 One or more arithmetic logic units (ALUs)
 Registers.

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THE CONTROL UNIT [CU]
 The control unit determines the order in which
instructions should be executed and controls the
retrieval of the proper operands.
 It interprets the instructions of the machine.

 The execution of each instruction is determined

by a sequence of control signals produced by the
control unit.
 Each operation caused by a control signal is
called a microoperation (MO).

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THE CONTROL UNIT
 Program is stored in memory as machine language
instructions, in binary format
 The task of the control unit is to execute programs by

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repeatedly:
 Fetch from memory the next instruction to be executed.
 Decode it, that is, determine what is to be done.
 Execute it by issuing the appropriate signals to the ALU,
memory, and I/O subsystems.
 Continues until the HALT instruction

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 ALUs perform all mathematical and Boolean
operations.

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 The registers are temporary storage locations to
quickly store and transfer the data and
instructions being used.

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 THE ALU SUBSYSTEM

 The ALU (Arithmetic/Logic Unit) performs

 mathematical operations (+, -, x, /, …)
logic operations (=, <, >, and, or, not, ...)

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

 In today's computers ALU integrated into the CPU

 Consists of:
 Circuits to do the arithmetic/logic operations.
 Registers (fast storage units) to store intermediate
computational results.
 Bus that connects the both.

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THE MEMORY
 The computer's memory is used to store program
instructions and data.

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 Two of the commonly used type of memories are
RAM (random-access memory) and ROM (read-
only memory).

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 MEMORY SUBSYSTEM
 Memory:
 Consists of many memory cells (storage units) of a
fixed size.

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Each cell has an address associated with it: 0, 1, …
 All accesses to memory are to a specified address.
A cell is the minimum unit of access (fetch/store a
complete cell).
 The time it takes to fetch/store a cell is the same
for all cells.

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 N
 Need to distinguish
between 0000000000000001
 the address of a memory cell 1 bit

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and the content of a memory 0
cell
1
 Memory width (W):
2
 How many bits is each memory
cell, typically one byte (=8 bits)
2N
 Address width (N): ...
 How many bits used to
represent each address,
determines the maximum
memory size = address space 2N-1
 If address width is N-bits, then 15
address space is 2N (0,1,...,2N-1)
W
 OPERATIONS ON MEMORY
 Fetch (address):
 Fetch a copy of the content of memory cell with the specified
address.
Non-destructive, copies value in memory cell.

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

 Store (address, value):

 Store the specified value into the memory cell specified by
address.
 Destructive, overwrites the previous value of the memory
cell.
 The memory system is interfaced via:
 Memory Address Register (MAR)
 Memory Data Register (MDR)
 Fetch/Store signal
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 STRUCTURE OF THE MEMORY SUBSYSTEM

 Fetch(address)
MAR MDR  Load address into MAR.

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F/S  Decode the address in MAR.
Memory  Copy the content of memory cell
Fetch/Store
decoder with specified address into MDR.
controller
circuit
 Store(address, value)
 Load the address into MAR.
 Load the value into MDR.
 Decode the address in MAR
 Copy the content of MDR into
...
memory cell with the specified
address.
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I/O SUBSYSTEM

 The I/O interfaces allow the computer's memory

to receive information and send data to output

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devices. Also, they allow the computer to
communicate to the user and to secondary
storage devices like disk and pen drives.

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INPUT/OUTPUT SUBSYSTEM
 Handles devices that allow the computer
system to:

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 Communicate and interact with the outside world
 Screen, keyboard, printer, ...
 Store information (mass-storage)
 Hard-drives, floppies, CD, tapes, …
 Mass-Storage Device Access Methods:
 Direct Access Storage Devices (DASDs)
 Hard-drives, floppy-disks, CD-ROMs, ...
 Sequential Access Storage Devices (SASDs)
 Tapes (for example, used as backup devices)
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 I/O CONTROLLERS

 Speed of I/O devices is slow compared to RAM

 RAM ~ 50 nsec.
 Hard-Drive ~ 10msec. = (10,000,000 nsec)

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 Solution:
 I/O Controller, a special purpose processor:
 Has a small memory buffer, and a control logic to control I/O device
(e.g. move disk arm).
 Sends an interrupt signal to CPU when done read/write.

 Data transferred between RAM and memory

buffer.
 Processor free to do something else while I/O
controller reads/writes data from/to device into
I/O buffer. 20
 STRUCTURE OF THE I/O SUBSYSTEM
Interrupt signal (to processor)
Data from/to memory

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I/O controller
I/O Buffer

Control/Logic

I/O device
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MICRO-OPERATIONS
 micro-operations perform basic operations on
data stored in one or more registers.

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 Eg.
 Shift
 Rotate
 Count (inc/dec)
 Clear
 Load

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CLASSIFICATION OF U-OPERATION

 The four basic classifications are:

1. Data transfer

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2. Arithmetic

3. Logical

4. Shift

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DATA TRANSFER U-OPERATION
 The data transfer u-operation again has two
types

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1. Register transfer u-operation
 This operation perform data transfer from register to
register.
 Eg. MOVE R1, R2
2. Memory transfer u 0peration
 The data transfer between register and memory.
 Eg. MOVE X, R1 [x=address of memory]

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ARITHMETIC U-OPERATION
 It performs the arithmetic u-operation on data.
 Eg:

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 ADD X, Y (Add content of memory locations X and
Y, and store back in memory location Y).

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LOGICAL U-OPERATIONS
 It performs the bit manipulation operations on
data of any register. like AND, OR, Compare etc.

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 Eg. ORL R1,R2

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SHIFT U-OPERATION
 It perform the uses to shift the data of register
either right or left.

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 Eg
SHL R1
SHR R1

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MACHINE LANGUAGE INSTRUCTIONS
 A machine language instruction consists of:
 Operation code, telling which operation to perform
 Address field(s), telling the memory addresses of the

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values on which the operation works.
 Example: ADD X, Y (Add content of memory
locations X and Y, and store back in memory
location Y).
 Assume: opcode for ADD is 9, and addresses X=99,
Y=100
Opcode (8 bits) Address 1 (16 bits) Address 2 (16 bits)
00001001 0000000001100011 0000000001100100
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INSTRUCTION SET DESIGN

 Two different approaches:

 Reduced Instruction Set Computers (RISC)

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 Instruction set as small and simple as possible.
 Minimizes amount of circuitry --> faster computers

 Complex Instruction Set Computers (CISC)

 More instructions, very complex
 Each instruction can do more work, but require more circuitry.

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TYPICAL MACHINE INSTRUCTIONS
 Notation:
 We use X, Y, Z to denote RAM cells

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 Assume only one register R (for simplicity)
 Use English-like descriptions (should be binary)

 Data Transfer Instructions

 LOAD X Load content of memory location X to
R
 STORE X Load content of R to memory location
X
 MOVE X, Y Copy content of memory location X to
loc. Y
(not absolutely necessary) 30
MACHINE INSTRUCTIONS (CONT.)
 Arithmetic
 ADD X, Y, Z CON(Z) = CON(X) + CON(Y)
 ADD X, Y CON(Y) = CON(X) + CON(Y)

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 ADD X R = CON(X) + R
 similar instructions for other operators, e.g. SUBTR,OR,
...
 Compare
 COMPARE X, Y
Compare the content of memory cell X to the content of
memory cell Y and set the condition codes (CCR)
accordingly.
 E.g. If CON(X) = R then set EQ=1
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MACHINE INSTRUCTIONS (CONT.)
 Branch
 JUMP X Load next instruction from memory
loc. X

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 JUMPGT X Load next instruction from memory
loc. X only if GT flag in CCR is
set, otherwise load statement from
next sequence loc. As usual.
 JUMPEQ, JUMPLT, JUMPGE, JUMPLE,JUMPNEQ
 Control
 HALT Stop program execution.

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 (C)_Nilesh Dubey
CONTROL UNIT DESIGN

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STRUCTURE OF THE CONTROL UNIT
 PC (Program Counter):
 stores the address of next instruction to fetch
 IR (Instruction Register):
 stores the instruction fetched from memory

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 Instruction Decoder:
 Decodes instruction and activates necessary
circuitry

PC IR

+1
Instruction
Decoder 34
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von Neumann
Architecture

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HOW DOES THIS ALL WORK TOGETHER?

 Program Execution:
 PC is set to the address where the first program

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instruction is stored in memory.
 Repeat until HALT instruction or fatal error
Fetch instruction
Decode instruction
Execute instruction
End of loop

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PROGRAM EXECUTION (CONT.)

 Fetch phase
 PC --> MAR (put address of PC into MAR)

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 Fetch signal (signal memory to fetch value into
MDR)
 MDR --> IR (move value to Instruction Register)
 PC + 1 --> PC (Increase address in program counter)

 Decode Phase
 IR -> Instruction decoder (decode instruction in IR)
 Instruction decoder will then generate the signals to
activate the circuitry to carry out the instruction

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PROGRAM EXECUTION (CONT.)

 Execute Phase
 Differs from one instruction to the next.

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END OF UNIT-1
(C)_Nilesh Dubey

UNIT-II
CONTROL UNIT ORGANIZATION
 Hardwired control unit,
 Micro and nano programmed control unit,
 Control Memory,
 Address Sequencing,
 Micro Instruction formats,
 Micro program sequencer,
 Microprogramming,
Arithmetic and Logic Unit
•Arithmetic Processor,
•Addition, subtraction,
•multiplication and division,
•Floating point and decimal arithmetic and arithmetic units, 40
•design of arithmetic unit.
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CONTROL UNIT
FUNCTIONS OF CONTROL UNIT

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DESIGN OF CONTROL UNIT

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HARDWIRE CONTROL UNIT

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HARDWIRE CONTROL UNIT

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HARDWIRE CONTROL UNIT

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ARCHITECTURE HARDWIRE CONTROL UNIT

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HARDWIRE CONTROL UNIT

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THE INSTRUCTION REGISTER

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THE INSTRUCTION REGISTER

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OTHER FUNCTIONS

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FOR EXAMPLE
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MICRO-PROGRAM CONTROL UNIT

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MICRO-PROGRAM CONTROL UNIT

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MICRO-PROGRAM CONTROL UNIT

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ACRCHITECTURE OF MICROPROGRAM CU

Control Address Register[CAR]

Fetch
uPS Decode

Add Micro
program
Next Address Information

Mul Memory

etc

Control DATA Register[CDR] To CU

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SIMPLIFIED FLOW

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Next-address Control Control Control Control
External
generator address memory data word
input
(sequencer) register (ROM) register

Next-address information

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WORKING
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ADVANTAGES :
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DISADVANTAGES
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COMPERISSION
ADDRESS SEQUENCING
 Address sequencing capabilities required in
control unit. It includes:

cpe 252: Computer Organization

 Incrementing uPS
 Unconditional or conditional branch, depending on
status bit conditions or Mode bit.
 Mapping from bits of instruction to address for
control memory
 Facility for subroutine call and return

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 Micro-instructions are stored in control memory in
groups.Each group specifies a routine
 Each computer instruction has its own micro-program
routine in the control memory.
 When power is turned on, an initial address is loaded
into CAR

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 This address is the address of the 1stmicroinstruction
that activates the instruction fetch routine.
 At the end of fetch routine, the instruction is in the
instruction register.
 Next, the control memory must go through the routine
that determines the effective address of the operand.
The effective address computation routine in the
control memory can be reached through a branch
micro-instruction. 64
 When the effective address computation routine is
completed, the address of the operand is available in
the memory address register.
 The next step is to generate micro-operation that
executes the instruction fetched from memory. Each
instruction has its own micro-program routine.

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 The transformation from the instruction code bits to
an address in control memory where the routine is
located is called a mapping process.
 After the execution of the instruction is completed. The
control must return to the fetch routine.

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 One simple mapping process that converts the 4-bit
operation code to a 7-bit address for control memory.

Fig: Mapping from instruction code to microinstruction address

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 Fig: Direct mapping

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ADDRESS SEQUENCER
Instruction code

Mapping
logic

Status Branch MUX

Multiplexers
bits logic select

Subroutine
Register
Control Address Register (SBR)
(CAR)

Incrementer

Control memory (ROM)

select a status
bit
Microoperations
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Branch address

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MICROPROGRAM EXAMPLE

MUX
10 0
Computer AR

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Address Memory
Configuration 2048 x 16
10 0
PC

MUX

15 0
6 0 6 0 DR
SBR CAR

Control memory Arithmetic

128 x 20 logic and
shift unit
Control unit
15 0 68
AC
MICROPROGRAM EXAMPLE
Computer instruction format
15 14 11 10 0
I Opcode Address

Four computer instructions

Symbol OP-code Description
EA is the effective address
ADD 0000 AC  AC + M[EA]
BRANCH 0001 if (AC < 0) then (PC  EA)
STORE 0010 M[EA]  AC
EXCHANGE 0011 AC  M[EA], M[EA]  AC

Microinstruction Format
3 3 3 2 2 7
F1 F2 F3 CD BR AD

F1, F2, F3: Microoperation fields

CD: Condition for branching
BR: Branch field
AD: Address field 69
 External
(MAP)

L
I 3 2 1 0
Input Load
I0 S1 MUX1 SBR
logic
T1 S0

1 Incrementer
I MUX2 Test
S
Z Select
Clock CAR

Control memory

Microops CD BR AD
... ...

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MICROINSTRUCTION FIELDS

CD Condition Symbol Comments

cpe 252: Computer Organization

00 Always = 1 U Unconditional branch
01 DR(15) I Indirect address bit
10 AC(15) S Sign bit of AC
11 AC = 0 Z Zero value in AC

BR Symbol Function
00 JMP CAR  AD if condition = 1
CAR  CAR + 1 if condition = 0
01 CALL CAR  AD, SBR  CAR + 1 if condition = 1
CAR  CAR + 1 if condition = 0
10 RET CAR  SBR (Return from subroutine)
11 MAP CAR(2-5)  DR(11-14), CAR(0,1,6)  0

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MICROINSTRUCTION FIELDS
F1 Microoperation Symbol F2 Microoperation Symbol
000 None NOP 000 None NOP
001 AC  AC + DR ADD 001 AC  AC - DR SUB
010 AC  0 CLRAC 010 AC  AC  DR OR

cpe 252: Computer Organization

011 AC  AC + 1 INCAC 011 AC  AC  DR AND
100 AC  DR DRTAC 100 DR  M[AR] READ
101 AR  DR(0-10) DRTAR 101 DR  AC ACTDR
110 AR  PC PCTAR 110 DR  DR + 1 INCDR
111 M[AR]  DR WRITE 111 DR(0-10)  PC PCTDR

F3 Microoperation Symbol
000 None NOP
001 AC  AC  DR XOR
010 AC  AC’ COM
011 AC  shl AC SHL
100 AC  shr AC SHR
101 PC  PC + 1 INCPC
110 PC  AR ARTPC
111 Reserved
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MICROPROGRAMMING
 In horizontal microcode, each control signal is
represented by a bit in the μ instruction Fewer
control store words of more bits per word

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 In vertical microcode, a set of true control signals
is represented by a shorter code.

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 UNIT-3

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I/O ORGANIZATION

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INPUT-OUTPUT INTERFACE
 Input-output interface provides a method for
transferring information between internal
storage and external I/O devices.

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 The purpose of the communication link is to
resolve the differences that exist between the
central computer and each peripheral.

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THE MAJOR DIFFERENCES ARE:

1. Peripherals are electromechanical and

electromagnetic devices and their manner of
operation is different from the operation of the CPU

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and memory, which are electronic devices. Therefore,
a conversion of signal values may be required.

2. The data transfer rate of peripherals is usually

slower than the transfer rate of the CPU, and
consequently, a synchronization mechanism may be
needed.

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3. Data codes and formats in peripherals differ from the
word format in the CPU and memory.

4. The operating modes of peripherals are different from

each other and each must be controlled so as not to
disturb the operation of other peripherals connected to

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the CPU.

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 To resolve these differences, computer systems include
special hardware components between the CPU and
peripherals to supervise and synchronize all input and
output transfers. These components are called
interface units

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Processor

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I/O COMMAND
 The function code is referred to as an VO command and is
in essence an instruction that is executed in the interface
and its attached peripheral unit.
They are classified as

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

◦ Control

◦ Status

◦ Data output

◦ Data input.

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I/O VERSUS MEMORY BUS
 Like the I/O bus, the memory bus contains data,
address, and read/write control lines. There are three
ways that computer buses can be used to
communicate with memory and I/O:

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1. Use two separate buses, one for memory and the
other for I/O.
2. Use one common bus for both memory and I/O but
have separate control lines for each.
3. Use one common bus for memory and I/O with
common control lines.

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ISOLATED I/O [I/O MAPPED I/O]

 In isolated I/O, a separate address space of the CPU is

reserved for I/O operations. This address space is
totally different from the address space used for

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memory devices.

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 In the isolated I/O configuration, the CPU has distinct input and
output instructions, and each of these instructions is associated
with the address of an interface register.
 For Input or Output Operation :
◦ places the address associated with the instruction into the common
address lines
◦ At the same time, enables the I/O read (for input) or I/O write (for
output) control line.

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 For Memory Operation :
◦ places the Memory address into the common address lines
◦ At the same time, enables the memory read or memory write
control line.

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MEMORY MAPPED I/O
 A single set of control lines
 No distinction between memory and IO transfer

 Memory and I/O Addresses share common address

space

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 Same input output instructions for both

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COMPARISON
ASYNCHRONOUS DATA TRANSFER
 Asynchronous data transfer between two
independent units requires control signals to
indicate the time at which data is being

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transmitted.

 There are two method for the control signal

 Strobe
 Handshaking

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SOURCE INITIATED STROBE FOR DATA
TRANSFER.

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DESTINATION INITIATED STROBE FOR DATA
TRANSFER.

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DISADVANTAGE OF STROBE METHOD
 The disadvantage of the strobe method is that
the source unit that initiates the transfer has no
way of knowing whether the destination unit has

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actually received the data item that was placed
in the bus.
 Similarly, a destination unit that initiates the
transfer has no way of knowing whether the
source unit has actually placed the data on the
bus.

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HANDSHAKING

 The handshake method solves this problem by

introducing a second control signal that provides
a reply to the unit that initiates the transfer.

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MODES OF TRANSFER
 Data transfer to and from peripherals may be
handled in one of three possible modes:

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1. Programmed I/O
2. Interrupt-initiated I/O
3. Direct memory access (DMA)

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 Programmed i/o operations are the result of i/o
instructions written in the computer program.

 Each data item transfer is initiated by an instruction in

the program.

Transferring data under program control requires

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
constant monitoring of the peripheral by the CPU.

 The CPU stays in a program loop until the i/o unit

indicates that it is ready for data transfer.

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 It can be avoided by using an interrupt facility and
special commands to inform the interface to issue
an interrupt request signal when the data are
available from the device.

 In direct memory access (DMA), the interface

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transfers data in/out of the memory unit through
the memory bus.

 The CPU Just initiates the transfer with the

starting address and the number of words needed
to be transferred.

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PROGRAMMED I/O
 In the programmed 110 method, the 110 device
does not have direct access to memory.

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 Used for small and dedicated systems.

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INTERRUPT-INITIATED I/O

 An alternative to the CPU constantly monitoring

the flag is to let the interface inform the
computer when it is ready to transfer data.

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INTERRUPT PRIORITY
 A priority interrupt is a system that establishes a
priority over the various sources to determine
which condition is to be serviced first when two

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or more requests arrive simultaneously.

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 A polling procedure is used to identify the
highest-priority source by software means.

 In this method there is one common branch

address for all interrupts.

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 The program that takes care of interrupts begins
at the branch address and polls the interrupt
sources in sequence.

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 The highest-priority source is tested first, and if
its interrupt signal is on, Then service provides
for this source.

 Otherwise, the next-lower-priority source is

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tested

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DAISY-CHAINING PRIORITY
 The daisy-chaining method of establishing
priority consists of a serial connection of all
devices that request an interrupt.

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 The device with the highest priority is placed in
the first position.

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ONE STAGE OF D-C PRIORITY ARRANGEMENT

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PARALLEL PRIORITY INTERRUPT
 The parallel priority interrupt method uses a
register whose bits are set separately by the
interrupt signal from each device.

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 Priority is established according to the position of
the bits in the register.

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PRIORITY INTERRUPT H/W

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IST= Interrupt status FF IEN= Interrupt Enable FF 107
I/O PROCESSOR

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108
CPU-IOP COMMUNICATION

109

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 UNIT-4

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MEMORY ORGANIZATION

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MEMORY HIERARCHY

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111
 AN EXAMPLE MEMORY HIERARCHY
Smaller, L0:
faster, registers CPU registers hold words retrieved
and from L1 cache.
costlier L1: on-chip L1
(per byte) cache (SRAM) L1 cache holds cache lines retrieved
storage from the L2 cache memory.
devices L2: off-chip L2
cache (SRAM) L2 cache holds cache lines
retrieved from main memory.

L3: main memory

Larger, (DRAM)
Main memory holds disk
slower, blocks retrieved from local
and disks.
cheaper local secondary storage
L4:
(per byte) (local disks)
storage Local disks hold files
devices retrieved from disks on
remote network servers.

L5: remote secondary storage

(tapes, distributed file systems, Web servers)
MEMORY HIERARCHY IN COMPUTER

Magnetic
tapes I/O Main

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processor memory
Magnetic
disks

CPU Cache
memory

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THE MAIN MEMORY
 It is a relatively large and fast memory used to
store programs and data during the computer
operation.

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 Integrated circuit RAM chips are available in two
possible operating modes, static and dynamic.

114
SRAM
 The static RAM consists essentially of internal
flip-flops that store the binary information.

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 The stored information remains valid as long as
power is applied to the unit.

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DRAM
 The dynamic RAM stores the binary information
in the form of electric charges that are applied to
capacitors.
 The stored charge on the capacitors tend to

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discharge with time and the capacitors must be
periodically recharged by refreshing the dynamic
memory.
 Refreshing is done by cycling through the words
every few milliseconds to restore the decaying
charge.

116
 The dynamic RAM offers reduced power
consumption and larger storage capacity in a
single memory chip.

 The static RAM is easier to use and has shorter

read and write cycles.

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 RAM integrated circuit chips, a portion of the
memory may be constructed with ROM chips.

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THE ROM OF MAIN MEMORY
 ROM is used for storing programs that are
permanently resident in the computer and do not
change in value once the production of the

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computer is completed.

 The ROM portion of main memory is needed for

storing an initial program called a bootstrap
loader.

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RAM AND ROM CHIPS
 RAM and ROM chips are available in a variety of
sizes.

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 If the memory needed for the computer is larger
than the capacity of one chip, it is necessary to
combine a number of chips to form the required
memory size.

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 A bidirectional bus in a RAM chip can be
constructed with three-state buffers.

Chip select 1 CS1

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Chip select 2 CS2
128 x 8
Read RD 8-bit data bus
RAM
Write WR

7-bit address AD 7

Typical RAM chip

CS1 CS2 RD WR Memory function State of data bus

0 0 x x Inhibit High-impedence
0 1 x x Inhibit High-impedence
1 0 0 0 Inhibit High-impedence
1 0 0 1 Write Input data to RAM
Read Output data from RAM 120
1 0 1 x
1 1 x x Inhibit High-impedence
 The capacity of the memory is 128 words of eight
bits (one byte) per word.

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 This requires a 7-bit address and an 8-bit
bidirectional data bus.

 The read and write inputs are sometimes

combined into one line labeled R/W.

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ROM CHIP
 A ROM chip is organized externally in a similar
manner.
 However, since a ROM can only read, the data

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bus can only be in an output mode.

Typical ROM chip

Chip select 1 CS1

Chip select 2 CS2
512 x 8 8-bit data bus
ROM

9-bit address AD 9
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MEMORY ADDRESS MAP
Example: 512 bytes RAM and 512 bytes ROM

Hexa Address bus

Component address 10 9 8 7 6 5 4 3 2 1

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RAM 1 0000 - 007F 0 0 0 x x x x x x x
RAM 2 0080 - 00FF 0 0 1 x x x x x x x
RAM 3 0100 - 017F 0 1 0 x x x x x x x
RAM 4 0180 - 01FF 0 1 1 x x x x x x x
ROM 0200 - 03FF 1 x x x x x x x x x

 The low-order lines in the address bus select the

byte within the chips and other lines in the
address bus select a particular chip through its
chip select inputs 123
MEMORY CONNECTIONS TO CPU
CPU
Address bus
16-11 10 9 8 7-1 RD WR Data bus

Decoder
3 2 1 0
CS1

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CS2

Data
RD 128 x 8
RAM 1
WR
AD7

CS1
CS2

Data
RD 128 x 8
RAM 2
WR
AD7

CS1
CS2

Data
RD 128 x 8
RAM 3
WR
AD7

CS1
CS2

Data
RD 128 x 8
RAM 4
WR
AD7

CS1 124
CS2
Data

1- 7 512 x 8
8
9 } AD9 ROM
AUXILIARY MEMORY
 The most common auxiliary memory devices used
in computer systems are magnetic disks and
tapes.

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 The important characteristics of any device are
its
1. Access mode
2. Access time
3. Transfer rate
Capacity

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4.
5. Cost.

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 The average time required to reach a storage
location in memory and obtain its contents is
called the access time.

 In electromechanical devices with moving parts

such as disks and tapes, the access time consists

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of a seek time required to position the read-write
head to a location and a transfer time required
to transfer data to or from the device.

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MAGNETIC DISK
 A magnetic disk is a circular plate constructed of
metal or plastic coated with magnetized material.

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 Often both sides of the disk are used and several
disks may be stacked on one spindle with
read/write heads available on each surface.
 All disks rotate together at high speed

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 The tracks are commonly divided into sections
called sectors.
 In most systems, the minimum quantity of
information which can be transferred is a sector.

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ASSOCIATIVE MEMORY
 Memory that is addressed by content rather
than by address; content addressable is often
used synonymously.

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 An Associative Memory permits its users to
specify part of a pattern or key and retrieve the
values associated with that pattern.

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TYPES OF ASSOCIATIVE MEMORY
 Auto Associative Memory
 The inputs and output vectors and are the same.

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(x||X)
 Hetero Associative Memory
 The inputs and output vectors s and t are different.

(y || z)

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 An auto-associative memory retrieves a
previously stored pattern that most closely
resembles the current pattern.

In a hetero-associative memory, the retrieved

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
pattern is in general, different from the input
pattern not only in content but possibly also in
type and format.

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CACHE MEMORY