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8251A Universal Synchronous Asynchronous Receiver Transmitter

The 8251A Universal Synchronous Asynchronous Receiver Transmitter (USART) is a peripheral device that converts parallel data from the CPU to serial data for transmission and serial data from external sources to parallel data for the CPU. It contains functional blocks for read/write control, transmission, reception, data buffering, and modem control. The transmitter sends data when its buffer is empty and transmission is complete when its output register is empty. The receiver accepts and converts serial to parallel data, using a double buffer system. Modem control allows interfacing to modems for telephone line communication. The device is configured using mode instructions to set functions and commands to set operations.

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43 views5 pages

8251A Universal Synchronous Asynchronous Receiver Transmitter

The 8251A Universal Synchronous Asynchronous Receiver Transmitter (USART) is a peripheral device that converts parallel data from the CPU to serial data for transmission and serial data from external sources to parallel data for the CPU. It contains functional blocks for read/write control, transmission, reception, data buffering, and modem control. The transmitter sends data when its buffer is empty and transmission is complete when its output register is empty. The receiver accepts and converts serial to parallel data, using a double buffer system. Modem control allows interfacing to modems for telephone line communication. The device is configured using mode instructions to set functions and commands to set operations.

Uploaded by

Akash Mittal
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as PPT, PDF, TXT or read online on Scribd
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8251A

UNIVERSAL SYNCHRONOUS ASYNCHRONOUS RECEIVER


TRANSMITTER

As a peripheral device of a microcomputer system, the


82C51A-2 receives parallel data from the CPU and transmits
serial data after conversion. This device also receives serial
data from the outside and transmits parallel data to the CPU
after conversion.
The functional blocks diagram of 8251
• Read/Write control logic
• Transmitter
• Receiver
• Data bus buffer
• Modem control.

Transmitter:
• If buffer register is empty, then TxRDY is goes to high.
• If output register is empty then TxEMPTY goes to high.
• The clock signal, TxC (low) controls the rate at which the bits
are transmitted by the USART.
Receiver:
• The receiver section accepts serial data and convert them into
parallel data
• The receiver section is double buffered, i.e., it has an input
register to receive serial data and convert to parallel, and a
buffer register to hold the parallel data.
• When the RxD line goes low, the control logic assumes it as a
START bit, waits for half a bit time and samples the line again.

Modem control:
• The MODEM control unit allows to interface a MODEM to
8251A and to establish data communication through MODEM
over telephone lines.
Control Words
There are two types of control word
1. Mode instruction (setting of function)
2. Command (setting of operation)

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