Introduction to

CMOS VLSI
Design

Circuit Families
 Outline
 Pseudo-nMOS Logic
 Dynamic Logic
 Pass Transistor Logic

Circuit Families CMOS VLSI Design Slide 2

 Introduction
 What makes a circuit fast?
– I = C dV/dt -> tpd  (C/I) DV
– low capacitance
– high current
– small swing B 4
A 4
 Logical effort is proportional to C/I Y
1 1
 pMOS are the enemy!
– High capacitance for a given current
 Can we take the pMOS capacitance off the input?
 Various circuit families try to do this…

Circuit Families CMOS VLSI Design Slide 3

 Pseudo-nMOS
 In the old days, nMOS processes had no pMOS
– Instead, use pull-up transistor that is always ON
 In CMOS, use a pMOS that is always ON
– Ratio issue
– Make pMOS about ¼ effective strength of
1.8
pulldown network 1.5
load
P/2 1.2
P = 24
Ids Vout 0.9

Vout 0.6
P = 14
16/2 0.3
P=4
Vin
0
0 0.3 0.6 0.9 1.2 1.5 1.8
Vin

Circuit Families CMOS VLSI Design Slide 4

 Pseudo-nMOS Gates
 Design for unit current on output
to compare with unit inverter. Y
 pMOS fights nMOS inputs
f

Inverter NAND2 NOR2

gu = gu = gu =
gd = g = gd =
gavg = Y gd = gavg =
avg
pu = A pu =
Y Y pu =
A pd = B pd = A B pd =
pavg = pavg = pavg =

Circuit Families CMOS VLSI Design Slide 5

 Pseudo-nMOS Gates
 Design for unit current on output
to compare with unit inverter. Y
 pMOS fights nMOS inputs
f

Inverter NAND2 NOR2

gu = gu = gu =
gd = 2/3 g = gd =
gavg = Y gd = gavg =
2/3 avg 2/3
pu = A 8/3 pu =
Y Y pu =
A 4/3 pd = B 8/3 pd = A 4/3 B 4/3 pd =
pavg = pavg = pavg =

Circuit Families CMOS VLSI Design Slide 6

 Pseudo-nMOS Gates
 Design for unit current on output
to compare with unit inverter. Y
 pMOS fights nMOS inputs
f

Inverter NAND2 NOR2

gu = 4/3 gu = 8/3 gu = 4/3

gd = 4/9 2/3 g = 8/9 gd = 4/9
gavg = 8/9 Y gd = 16/9 gavg = 8/9
2/3 avg 2/3
pu = A 8/3 pu =
Y Y pu =
A 4/3 pd = B 8/3 pd = A 4/3 B 4/3 pd =
pavg = pavg = pavg =

Circuit Families CMOS VLSI Design Slide 7

 Pseudo-nMOS Gates
 Design for unit current on output
to compare with unit inverter. Y
 pMOS fights nMOS inputs
f

Inverter NAND2 NOR2

gu = 4/3 gu = 8/3 gu = 4/3

gd = 4/9 2/3 g = 8/9 gd = 4/9
gavg = 8/9 Y gd = 16/9 gavg = 8/9
2/3 avg 2/3
pu = 6/3 A 8/3 pu = 10/3
Y Y pu = 10/3
A 4/3 pd = 6/9 B 8/3 pd = 10/9 A 4/3 B 4/3 pd = 10/9
pavg = 12/9 pavg = 20/9 pavg = 20/9

Circuit Families CMOS VLSI Design Slide 8

 Pseudo-nMOS Design
 Ex: Design a k-input AND gate using pseudo-nMOS.
Estimate the delay driving a fanout of H
Pseudo-nMOS
 G= In1 1
Y
 F= H
Ink 1
 P=
 N=
 D=

Circuit Families CMOS VLSI Design Slide 9

 Pseudo-nMOS Design
 Ex: Design a k-input AND gate using pseudo-nMOS.
Estimate the delay driving a fanout of H
Pseudo-nMOS
 G = 1 * 8/9 = 8/9 In1 1
Y
 F = GBH = 8H/9 H
Ink 1
 P = 1 + (4+8k)/9 = (8k+13)/9
 N=2
4 2 H 8k  13
 D = NF + P = 3  9
1/N

Circuit Families CMOS VLSI Design Slide 10

 Pseudo-nMOS Power
 Pseudo-nMOS draws power whenever Y = 0
– Called static power P = I•VDD
– A few mA / gate * 1M gates would be a problem
– This is why nMOS went extinct!
 Use pseudo-nMOS sparingly for wide NORs
 Turn off pMOS when not in use

en
Y
A B C

Circuit Families CMOS VLSI Design Slide 11

 Dynamic Logic
 Dynamic gates uses a clocked pMOS pullup
 Two modes: precharge and evaluate

2 2/3  1
A Y Y Y
1 A 4/3 A 1

Static Pseudo-nMOS Dynamic

 Precharge Evaluate Precharge

Circuit Families CMOS VLSI Design Slide 12

 The Foot
 What if pulldown network is ON during precharge?
 Use series evaluation transistor to prevent fight.

 
precharge transistor
 Y Y
Y inputs inputs
A f f
foot

footed unfooted

Circuit Families CMOS VLSI Design Slide 13

 Logical Effort
Inverter NAND2 NOR2

 1
Y
 1  1
A 2
unfooted Y Y
A 1 B 2 A 1 B 1
gd = gd = gd =
pd = pd = pd =

 1
Y
 1  1
A 3
Y Y
footed A 2 B 3 A 2 B 2
gd = gd = gd =
2 pd = 3 pd = 2 pd =

Circuit Families CMOS VLSI Design Slide 14

 Logical Effort
Inverter NAND2 NOR2

 1
Y
 1  1
A 2
unfooted Y Y
A 1 B 2 A 1 B 1
gd = 1/3 gd = 2/3 gd = 1/3
pd = 2/3 pd = 3/3 pd = 3/3

 1
Y
 1  1
A 3
Y Y
footed A 2 B 3 A 2 B 2
gd = 2/3 gd = 3/3 gd = 2/3
2 pd = 3/3 3 pd = 4/3 2 pd = 5/3

Circuit Families CMOS VLSI Design Slide 15

 Monotonicity
 Dynamic gates require monotonically rising inputs
during evaluation

– 0 -> 0
– 0 -> 1 A

– 1 -> 1
– But not 1 -> 0 violates monotonicity
during evaluation
A

 Precharge Evaluate Precharge

Output should rise but does not

Circuit Families CMOS VLSI Design Slide 16

 Monotonicity Woes
 But dynamic gates produce monotonically falling
outputs during evaluation
 Illegal for one dynamic gate to drive another!

A=1

  Precharge Evaluate Precharge

Y
X
A
X

Circuit Families CMOS VLSI Design Slide 17

 Monotonicity Woes
 But dynamic gates produce monotonically falling
outputs during evaluation
 Illegal for one dynamic gate to drive another!

A=1

  Precharge Evaluate Precharge

Y
X
A
X
X monotonically falls during evaluation
Y
Y should rise but cannot

Circuit Families CMOS VLSI Design Slide 18

 Domino Gates
 Follow dynamic stage with inverting static gate
– Dynamic / static pair is called domino gate
– Produces monotonic outputs
 Precharge Evaluate Precharge

domino AND
W

W X Y Z X
A
Y
B C

Z

dynamic static
 
NAND inverter  
A W X A X
H Y =
B H Z B Z
C C

Circuit Families CMOS VLSI Design Slide 19

 Domino Optimizations
 Each domino gate triggers next one, like a string of
dominos toppling over
 Gates evaluate sequentially but precharge in parallel
 Thus evaluation is more critical than precharge
 HI-skewed static stages can perform logic


S0 S1 S2 S3
D0 D1 D2 D3
Y
H


S4 S5 S6 S7
D4 D5 D6 D7

Circuit Families CMOS VLSI Design Slide 20

 Dual-Rail Domino
 Domino only performs noninverting functions:
– AND, OR but not NAND, NOR, or XOR
 Dual-rail domino solves this problem
– Takes true and complementary inputs
– Produces true and complementary outputs

sig_h sig_l Meaning

0 0 Precharged Y_l  Y_h

inputs
0 1 ‘0’ f f

1 0 ‘1’ 

1 1 invalid

Circuit Families CMOS VLSI Design Slide 21

 Example: AND/NAND
 Given A_h, A_l, B_h, B_l
 Compute Y_h = A * B, Y_l = ~(A * B)

Circuit Families CMOS VLSI Design Slide 22

 Example: AND/NAND
 Given A_h, A_l, B_h, B_l
 Compute Y_h = A * B, Y_l = ~(A * B)
 Pulldown networks are conduction complements

Y_l  Y_h
= A*B A_h = A*B
A_l B_l B_h

Circuit Families CMOS VLSI Design Slide 23

 Example: XOR/XNOR
 Sometimes possible to share transistors

Y_l  Y_h
= A xnor B A_h A_l A_l A_h = A xor B
B_l B_h

Circuit Families CMOS VLSI Design Slide 24

 Leakage
 Dynamic node floats high during evaluation
– Transistors are leaky (IOFF  0)
– Dynamic value will leak away over time
– Formerly miliseconds, now nanoseconds!
 Use keeper to hold dynamic node
– Must be weak enough not to fight evaluation
weak keeper
 1 k
X
H Y
A 2
2

Circuit Families CMOS VLSI Design Slide 25

 Charge Sharing
 Dynamic gates suffer from charge sharing



Y A
A x CY
Y
B=0 Cx

Circuit Families CMOS VLSI Design Slide 26

 Charge Sharing
 Dynamic gates suffer from charge sharing



Y A
A x CY
Y
B=0 Cx Charge sharing noise

Vx  VY 

Circuit Families CMOS VLSI Design Slide 27

 Charge Sharing
 Dynamic gates suffer from charge sharing



Y A
A x CY
Y
B=0 Cx Charge sharing noise

CY
Vx  VY  VDD
C x  CY

Circuit Families CMOS VLSI Design Slide 28

 Secondary Precharge
 Solution: add secondary precharge transistors
– Typically need to precharge every other node
 Big load capacitance CY helps as well

secondary
 precharge
Y transistor
A x
B

Circuit Families CMOS VLSI Design Slide 29

 Noise Sensitivity
 Dynamic gates are very sensitive to noise
– Inputs: VIH  Vtn
– Outputs: floating output susceptible noise
 Noise sources
– Capacitive crosstalk
– Charge sharing
– Power supply noise
– Feedthrough noise
– And more!

Circuit Families CMOS VLSI Design Slide 30

 Domino Summary
 Domino logic is attractive for high-speed circuits
– 1.5 – 2x faster than static CMOS
– But many challenges:
• Monotonicity
• Leakage
• Charge sharing
• Noise
 Widely used in high-performance microprocessors

Circuit Families CMOS VLSI Design Slide 31

 Pass Transistor Circuits
 Use pass transistors like switches to do logic
 Inputs drive diffusion terminals as well as gates

 CMOS + Transmission Gates:

– 2-input multiplexer
– Gates should be restoring
S S

A A

S Y S Y

B B

S S

Circuit Families CMOS VLSI Design Slide 32

 LEAP
 LEAn integration with Pass transistors
 Get rid of pMOS transistors
– Use weak pMOS feedback to pull fully high
– Ratio constraint

S
A
S L Y
B

Circuit Families CMOS VLSI Design Slide 33

 CPL
 Complementary Pass-transistor Logic
– Dual-rail form of pass transistor logic
– Avoids need for ratioed feedback
– Optional cross-coupling for rail-to-rail swing

S
A
S L Y
B
S
A
S L Y
B

Circuit Families CMOS VLSI Design Slide 34