Week 10 RTOS Real Time Operating Systems v1.2
Week 10 RTOS Real Time Operating Systems v1.2
CENG--336
336
Introduction
Introduction to
to Embedded
Embedded
Systems
Systems Development
Development
Introduction to
RTOS – Real-time Operating Systems
Based on Lecture Notes by Tuna Tuğcu
Three Central Concepts
Concurrency – several concurrent
threads of execution
Reactivity – external input is reacted to
rather than requested
Real time – timing behavior of reactions
is important
Disadvantages
Can’t handle sporadic events
Everything must operate in lockstep
Code must be scheduled manually
Background
ISR ISR
Foreground
ISR
(more
important)
= do a = do output
computation to device 2
2. Interrupt 3. Processor
occurs state saved
4. Interrupt routine
runs
6. Processor state
restored 5. Interrupt routine
terminates
7. Normal
program
execution
resumes
ISR
When a task relinquishes the CPU, the highest priority task in the list of tasks
waiting for the CPU executes
But lower-priority task cannot lose the CPU to a higher-priority task until it is
done., The higher priority task waits for the other to relinquish the CPU
The lower priority task can still be interrupted by an ISR; but it resumes
processing after the ISR returns, and the higher priority task still only gets the
CPU when the lower priority task has relinquished it.
A non-preemptive kernel can suffer from “priority inversion” problems, where a
low-priority task can take a long time and lock out a more important higher
priority task.
ISR
In this case, a higher priority task can grab the CPU off the lower
priority task as soon as it becomes ready to execute, before the
lower priority task relinquishes it. The lower-priority task waits
(among other tasks of equal priority) to resume.
If the higher priority task becomes ready to run while an ISR
(which interrupted the lower priority task) is executing, it gets
the CPU on return from the ISR, and the lower priority task must
wait for the higher one to relinquish the CPU before it can
resume.
interrupted
ISR
task
ready running completion
context switch
dead
Execution Deadline
Initiation time
Time
Period
U= (ci / pi)
No schedule can possibly exist if U > 1
No processor can be running 110% of the time
Fundamental result:
RMS schedule always exists if U < n * (2 1/n – 1)
Proof based on case analysis (P1 finishes before P2)
Interrupt handlers
Gather data, acknowledge interrupt as
quickly as possible
Cooperative multitasking
But programs don’t like to cooperate
Task 2 (medium)
Task 3 (low)
1 2 3 4 5 6
This can happen even in Preemptive kernels. Eg: 3 task with low, medium, high priority:
Task 3 (low) runs while 1 and 2 wait for some event. At point 1, 3 acquires an exclusive lock on a
resource.
At point 2, task 1 becomes ready and preempts task 3
At point 3, task 1 wants the resource but it is still locked by task 3; so task 1 waits and task 3
resumes
At point 4, task 2 becomes ready and starts running, preempting task 3.
Task 2 runs until done, point 5 and task 3 resumes, not task 1 because the latter is still waiting for
the resource locked by task 3
Finally at point 6, task 3 releases the resource and task 1 acquires it and can run.
Effectively task 1 has been trapped at the level of task 3 until 3 releases the resource.
Task 2 (medium)
Task 3 (low)
1 2 3 4 5 6
wait(s) { signal(s) {
if (s > 0) increment s by 1;
decrement s by 1; }
else {
wait until s > 0
decrement s by 1;
}
}
CENG-336 Introduction to Embedded Systems Development 97
Semaphores for Sync.
Using a semaphore to synchronise a tasks on a condition
task1 needs condition = true to proceed; task 2 is signalling process
(see below)
Assume semaphore variable consyn initialised to 0
When task 1 executes wait on a 0 semaphore, it will be delayed until
task 2 executes the signal. This sets consyn to 1 and the wait can
succeed. Task 1 can continue and consyn will be decrmeneted to 0
If task 2 executes signal first, consyn will = 1 and the wait() will will not
delay task1.
Task 1 could be a task requiring an exclusive lock on a resource; task 2
could signal on releasing the resource.
task1 { task2 {
.... ...
wait(consyn); signal(consyn);
.... ....
} }
task1 { task2 {
while (...) { while (...) {
wait(mutex); wait(mutex);
/*critical section*/ /*critical section*/
signal(mutex); signal(mutex);
/*non-critical sect*/ /*non-critical sect*/
} }
} }
CENG-336 Introduction to Embedded Systems Development 99
Message Queues & Events
We would like tasks to be able to communicate
asynchronously
Tasks to send and receive messages
ISRs to send messages
Discipline normally FIFO
Events
Tasks can be synchronised with occurrence of multiple
events
Occurrence of an event will signal a list of tasks; the
highest-priority task of these will me made ready to
run.