EE4S23 – ASIC Technology

and Test Systems

Lecture 2 - ASIC Types and Economics

 Overview of Lecture
• Types of ASICs
– History
– Full-custom
– Standard-cell
– Gate-array
• Channelled
• Channelless
• Structured
 Overview of Lecture
• Types of ASICs
– Programmable Logic Devices
– Field Programmable Gate Arrays
• Economics of ASICs
– Comparison between ASIC technologies
– Product Cost
– ASIC fixed costs
– ASIC variable costs
 History of ICs
• ASIC – Application Specific Integrated Circuit,
not standard ICs
• Early 1970s, Small Scale Integration (SSI),
few gates (tens of transistors). Based on
bipolar technologies, TTL and ECL
• Medium Scale Integration (MSI), larger logic
functions (e.g. counters, decoders). Based on
MOS technologies; NMOS, PMOS and
CMOS
 History of ICs
• Large Scale Integration (LSI), early
microprocessors
• Very Large Scale Integration (VLSI), 64-
bit microprocessors
 Trends in ASICs
• Traditionally, the cost/function in an IC is
reduced by 25% to 30% a year.
• To achieve this, the number of functions/IC
has to be increased. This demands for:
– Increase of the transistor count
– Decrease of the feature size (contains the area
increase and improves performance)
– Increase of the clock speed

ASIC Technology – Lecture 3

 Trends in ASICs
• Increase productivity:
– Increase equipment throughput
– Increase manufacturing yields
– Increase the number of chips on a wafer:
• reduce the area of the chip: smaller feature size &
redesign
– Use the largest wafer size available
• Example of a cost effective product (typically
DRAM): the initial IC area is reduced to 50%
after 3 years and to 35% after 6 years.
ASIC Technology – Lecture 3
ASIC Technology – Lecture 3
 ASIC features
• NAND gate comprises of 4 transistors
• Multiply gate count by 4 to get transistor
count
• Feature size (roughly half the length of
the smallest transistor), measured in
microns
• Lamda, λ is used to denote the smallest
feature size
 Types of ASICs
• ICs fabricated from thin circular silicon wafers
• Each wafer contains hundreds of dies (dice)
• Transistors and wiring made from may layers
(between 10 to 15) built on top of each other
• Layers are generated by masks, like a
photographic slide
• First half of masks define the transistors
• Last half of masks define the interconnects
 Types of ASICs
• Full-Custom
– All (or most) logic cells and mask layers
are customised
– Most expensive to manufacture and design
– Highest level of integration and design
density
– Manufacturing lead time ~ 8 weeks
 Types of ASICs
• Full-Custom
– Designer has total freedom in placement
and routing
– Custom design cells perform optimally for
the required function
– Power consumption can be reduced by
removing unnecessary cells
– Analogue designs often require a full
custom design flow
 Types of ASICs
• Standard Cell (or CBIC)
– IC has rows of standard cells (from library)
– Can be used in conjunction with megacells (e.g.
microcontrollers, megafunctions, etc)
– Designer only defines the placement and
interconnect of standard cells
– Advantage of standard cell is that designers can
save time, money and reduce risk by using
predesigned, pretested and precharacterised
library cells
 Types of ASICs
• Standard Cell
– All mask layers are customisable
– Custom blocks can be embedded
– Manufacturing lead time ~ 8 weeks
– Each cell in library is designed using full
custom techniques
– Cells fit together like ‘bricks of a wall’
Standard Cell (example
floorplan)
Standard Cell (example cell)
Standard Cell Layout (real world)

Very small section of design

 Types of ASICs
• Gate-array
– All transistors are predefined on the wafer
– Only metal (interconnect) layers are
defined by the designer
– Designer chooses from a library of
predefined and precharacterised logic cells
– Cells in library often called macros
Gate Array (real world)
 Types of ASICs
• Gate-array
– Wafers can be stock-piled as only metal
layers are added (plus passivation)
– Manufacturing time ~ few days to few
weeks
– Initial fabrication costs are shared for each
customer, this reduces the cost of gate-
array versus standard cell (and full custom)
 Types of ASICs
• Gate array
– Channeled gate array
• Only interconnect is customised
• Interconnect uses predefined spaces between rows of
base cells
• Manufacturing lead time is between two days and two
weeks
• Similar to standard cell, both use rows of cells separated
by channels used for interconnect
• Difference is that space for interconnect is fixed in height
for channeled gate array
Channeled Gate Array
 Types of ASICs
• Gate array
– Channelless Gate Array
• Also called sea of gates
• Only the top mask layers are customised – the
interconnect
• Manufacturing time ~ 2days to 2 weeks
• No predefined areas set aside for routing
between cells, instead routing passes over top
of cells
• Higher logic density than channeled gate array
Channelless Gate Array
 Types of ASICs
• Gate array
– Structured Gate Array
• Combines some of standard cell features with gate array
• Area of IC set aside for a specific function (e.g. RAM)
• Only interconnect is customised
• Custom blocks can be embedded
• Manufacturing time ~ 2 days to 2 weeks
• Has the density of cell based ICs together with the
reduced costs of gate array
Structured Gate Array
 Types of ASICs
• Programmable Logic Devices
– Standard devices (PLD, PAL, CPLD) sold in high
volumes
– No customised mask layers or logic cells
– Fast design turnaround
– Single large block of programmable interconnect
– Matrix of macrocells that usually consist of
programmable array logic followed by a flip-flop or
latch
Programmable Logic Devices
 Types of ASICs
• Field Programmable Gate Array
– Step up in complexity over programmable
logic
– No customisable mask layers
– Method of programming the basic logic
cells and the interconnect
– Core is a regular array of programmable
logic cells that can be used to implement
combinational as well as sequential logic
 Types of ASICs
• Field Programmable Gate Array
– Matrix of programmable interconnect
surrounds the basic logic cells
– Programmable I/O cells surround the core
– Design turnaround in a few hours
Field Programmable Gate Array
Xilinx Spartan 3 – die image

Notice the regularity

 Comparing Technologies -
Density (gates per chip)
• Highest to lowest density: Full Custom, Standard
Cell, Gate Array, FPGAs, CPLD, PLD
• Full Custom, Standard Cell, Gate Array are called
ASIC technologies (Application Specific Integrated
Circuit). Large Density gap between ASIC
technologies and Programmable logic technologies
(FPGAs, CPLD, PLD).
• Highest end FPGA density is now equal to low-end
ASIC density (i.e., hundreds of thousands of gates
with embedded SRAMs).
Comparing Technologies - Speed
• Highest to lowest performance: Full Custom,
Standard Cell, Gate Array, PLDs, CPLDs,
FPGAs.
• Again, large performance gap between ASIC
technologies and programmable
technologies.
• Performance of programmable technologies
is in reverse order of their densities.
Comparison
Design effort v Performance
 Summary
• Full custom can give best density and
performance
• Faster design time and ease of design are
principle advantages of gate array and
standard cell over full custom.
• Fast fabrication time and lower cost are
principle advantages of gate arrays over
standard cell.
• Gate arrays offer much higher density over
FPGAs and are cheaper than FPGAs in
volume production.
 Summary (cont.)
• FPGAs principle advantage over gate arrays
is 'instant' fabrication time (programmed on
the desktop). FPGAs are also cheaper than
gate arrays in low volume. Densities are
reaching 100's of thousands of gates/chip.
Can be used to prototype full
custom/standard cell designs.
• PLDs still hold a speed advantage over most
FPGAs and are useful primarily for high
speed decoding and speed critical glue logic.