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Arm Processors: By, Nimmi James S7 Ec-A Roll No:46

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145 views28 pages

Arm Processors: By, Nimmi James S7 Ec-A Roll No:46

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james_nimmi
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© Attribution Non-Commercial (BY-NC)
We take content rights seriously. If you suspect this is your content, claim it here.
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ARM PROCESSORS

By,
NIMMI JAMES
S7 EC-A
ROLL NO:46
CONTENTS
 ARM History
 Applications
 ARM Members
 Architecture
 Arm CONTROLLERS
 INSTRUCTIONS
Brief history of ARM

 Founded in 1990.
 ARM -Advanced Risc Machines
 32bit RISC processor from ARM Holdings.
 ARM Holding is a joint venture between
Acron computers, Apple computers and VLSI
Technology.
ARM PARTNER
 ARM Holdings - supplies ARM processor Core
 doesn’t manufacture ARM processor chips .
 designs the ARM processor core
 licences its ARM IP to their networked
partners.
ARM POWERED PRODUCTS
Why ARM here?

 most licensed ;widespread processor cores in


the world
 low power consumption( 3.0v to 3.6v)
 reasonable performance
 used in portable devices like mobilephones.
ARM MEMBERS
• ARM 1 • ARM9
• ARM 2 • ARM10
• ARM3 • ARM11
• ARM4
• ARM5
• ARM6
ARM11™ Series - Performance
• ARM7 processors based on the
• ARM8 ARMv6 architecture
• STRONG ARM ARM9™ Series- Popular
processors based on the the
ARMv5 architecture
ARM7™ Series- Classic
processors for general
purpose applications 
OPERATING MODES
1. User Mode- Normal program execution state
2. Fast Interrupt Processing (FIQ) Mode - when a high
priority interrupt is raised.
3. Normal Interrupt Processing (IRQ) Mode- when a
normal priority interrupt is raised.
4. Supervisor /Software Interrupt Mode- Protected mode
for operating system support .
Eg: when reset /software interrupt instruction is
executed.
5. Abort Mode - when data or instruction fetch is aborted.
6. System Mode – for running Operating system tasks.
7. Undefind Instruction Mode-when processor tries to
execute an undefined instruction.
REGISTERS OF ARM
ARM7 register set
 thirty-seven 32bit registers.
 30 are general purpose registers
 16 general purpose registers(R0 to R15) are available in
ARM-mode (user mode)
• Register structure depends on mode of operation
• R13 - Stack Pointer (SP)
• R14 - subroutine Link Register for branch and link
instructions
• R15 - Program Counter (PC)
• R16 - state register (CPSR, Current Program Status Register)
CPSR-Current program status register
• CPSR holds execution status of the processor,processor operation mode,interrupt enable bit
status,etc.

B31 B30 B29 B28 B27 B25 to B26 B24 B8 to B7 B6 B5 B0 to


B23 B4

N Z C V Q J I F T Mode
Select

• N=1:The result of ALU operation is negative.


• Z=1:The result of ALU operation is zero.
• C=1:carry generated as a result of the operation executed in ALU.
• V=1:ALU operation resulted in overflow.
• ‘J’ bit : whether the processor is Jazelle state or not .
• ‘T ‘ bit : whether the ARM is using 32-bit ARM instructions or 16-bit Thumb
instructions.
• ‘I’ and ‘F’ flags are used for disabling interrupts.
If I= 1,NORMAL interrupts are disabled.
If F=1 ,FAST interrupts are disabled.
Pipelines
splitting one task in to multiple subtasks
executing the subtasks of successive tasks parallely
in multiple hardware units or sections.
ARM processors:
• FIRST GENERATION-3 stage pipelining
• ARM7 – 3 stage pipelining
• ARM9 – 5 stage
• ARM10 – 6 stage
• ARM11 – 8 stage
ARM7TDMI

• TDMI = (?)
 Thumb instruction set
 Debug-interface (JTAG/ICEBreaker)
 Multiplier (hardware)
 Interrupt (fast interrupts)
• The most used ARM-version
DSP enhancement

• To improve the ARM architecture for


digital signal processing and multimedia
applications, a few new instructions were
added to the set.
• These are signified by an "E" in the name of
the ARMv5TE and ARMv5TEJ architectures. E-
variants also imply T,D,M and I.
ARM® Jazelle Technology

• Provides a highly-optimized implementation of


the Java Virtual Machine (JVM).
• Speeds up execution times.
• Provides consumers with an enriched user
experience on their mobile devices.
ARM Media Extensions

•streaming media performance (film,


video phone, music and more)
•more human-oriented interfaces
(voice and handwriting recognition)
Architecture versions and variants

• Six major versions of the instruction set


have been defined to date, denoted by
• ARMv1,ARMv2,ARMv3-26-bit architecture.
• ARMv4
• ARMv5
• ARMv6
ARM ARCHITECTURE
Architect THUMB DSP Jazelle Media
ure

ARMv4 X
T
ARMv5 X X
TE
ARMv5T X X X
EJ

ARMv6 X X X X
General Purpose Microprocessor
System
DATA BUS

CPU
General
Purpose SERIAL
I/O
RAM ROM TIMER COM
Micro- PORT
PORT
processor

ADDRESS BUS
MICROCONTROLLERS based on
ARM7TDMI
• The LPC2131/32 microcontrollers are based
on 16/32 bit ARM7TDMI
• One 8 channel 10-bit A/D Converters ,with
conversion time as low as 2.44micro sec.
• MULTIPLE Serial interfaces.
• Two 32-bit timer/counters.
COMPARISON
ARM Power consumption 5v
1. Low power
consumption ( 3.0v Low speed
to 3.6v). Do not support DSP
2. High speed. Supports 8 bit
3. Supports DSP,Media. instruction
4. Supports 8/16/32 bit
instructions. Low cost
5. High cost.
PIC
ARM
INSTRUCTIONS
The Instruction Set Architecture(ISA) of supports
different types of Instruction sets,namely:
1. ARM Instruction Set-The original ARM
instruction.Here all instruction are 32bit wide and
word aligned.since all instructions are word
aligned,one single fetch reads four 8bit memory
locations.
2. Thumb Instruction Set-These instructions can be
considered as a 16bit compressed form of the
orginal 32bit ARM instruction. These
instructions can be executed by decompressing the
instruction to the original 32bit ARM instructions
3.Jazelle Instruction Set- Jazelle is a technique
that allows Java Bytecode to be executed
directly in the ARM architecturea.
4.Data Processing Instruction-The data
processing instructions include
OPERATION CATEGORY INSTRUCTION

Arithmetic ADD,ADC,SUB,SBC,RSB,RSC

Logical AND,ORR,EOR,BIC

Comparison CMP,CMN,TST,TEQ

Data movement MOV,MVN


5.Branching Instructions-diverts the program
flow.BX,B,BL etc.
6.Multiplication Instruction-MUL,MLA,MLL ,MLAL.
7.Co-Processor Specific Instructions- ARM does
not execute certain instructions and lets a co-
processor to execute these instructions.
CDP,LDC,STC,MRC,MCR.
CONDITIONAL INSTRUCTIONS
CONDITIO DESCRIPTION FLAG TO
N CODE TEST
• All ARM instructions
EQ Check the equality Z==1 are conditional.
NE Check the non-equality Z==0

CS/HS Carry C==1


• Std form
CC/LO No carry C==0
opcode<condition
MI Negative N==1
code>operands
PL Positive or zero N==0

VS Overflow V==1
• eg 1: ADDAL r0,r1,r2
VC No overflow V==0 • eg 2:ADDEQ r0,r1,r2
AL Execute always None
SUMMARY

 32-bit RISC-processor core (32-bit instructions)


 37 pieces of 32-bit integer registers (16 available)
 Pipelined (ARM7: 3 stages)
 Cached (depending on the implementation)
 Von Neuman-type bus structure (ARM7), Harvard
(ARM9)
 8 / 16 / 32 -bit data types
 7 modes of operation (usr, fiq, irq, svc, abt, sys,
und)
 Simple structure
 Good speed/powerconsumption ratio
REFERENCES
• Computer organisation and architecture-carl
hamacher.
• The 8051 microcontrollers-Muhammad ali
mazidi
• www.armprocessorsmanuval.com
• www.arm.architecture.com
• www.arm7processor.com
• www.arm7processors,family.com
THANK YOU

THANK YOU

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