Test Power

Copyright Agarwal & Srivaths, 2007 Low-Power Design and Test, Lecture 8
 Outline

 Test Power Problem: Background and Basics

 Increasing Test Power Concerns
 Aspects of Test Power Dissipation
 DFT techniques targeting test power
 Power-aware ATPG
 Power Analysis Methodologies and Issues

Copyright Agarwal & Srivaths, 2007 Low-Power Design and Test, Lecture 8 2
 Test Power Problem*

 A circuit is designed for certain function. Its design must allow the power
consumption necessary to execute that function/application.
 Power buses are laid out to carry the maximum current necessary for the
function.
 Heat dissipation of package conforms to the average power consumption
during the intended function.

Manufacturing test mode can be/should be viewed

as another mode of operation for the circuit with
respect to power dissipation.

* See [Ravi-VDAT07,Ravi-ITC07] for more information on test power

Copyright Agarwal & Srivaths, 2007 Low-Power Design and Test, Lecture 8 3
 Testing Differs from Function: Functional Mode

Other chips

System System
VLSI chip outputs
inputs

system

Functional inputs Functional outputs

Copyright Agarwal & Srivaths, 2007 Low-Power Design and Test, Lecture 8 4
 Testing Differs from Function: Test Mode

Packaged or unpackaged DUT output for

device under test (DUT) comparison with
expected response
stored in ATE
VLSI chip
Test vectors:
Pre-generated
and stored in Clock Power
ATE
Automatic Test Equipment (ATE):
Control processor, vector memory,
timing generators, power module,
response comparator

Copyright Agarwal & Srivaths, 2007 Low-Power Design and Test, Lecture 8 5
 Scan Testing

Sequential Circuit with Scan

Primary Primary
Scan Flip-Flop
inputs outputs
Combinational
logic D 1 SO

mux
DFF Q
SD 0
Scan-out SE Scan flip-flop
SO
Q Scan D
flip-
Scan enable flops
SE An example scan based test
Scan-in
During response shift-out, next pattern can be
SI concurrently shifted in.

Shift-In Capture Shift-Out

• time
Copyright Agarwal & Srivaths, 2007 Low-Power Design and Test, Lecture 8 6
 Testing Differs from Function: Functional Inputs
vs. Test Vectors

 Functional inputs:  Test vectors:

■ Functionally meaningful ■ Functionally irrelevant signals
signals ■ Generated by software to test
■ Generated by circuitry faults
■ Can be random or
■ Restricted set of inputs pseudorandom
■ May be optimized to reduce
■ May have been optimized to test time; can have high logic
reduce logic activity and power activity
■ May use testability logic for
test application

Copyright Agarwal & Srivaths, 2007 Low-Power Design and Test, Lecture 8 7
 Terminology*
 Design-for-test (DFT): Modifications to the circuit for facilitating test. e.g.
scan flip-flop insertion
 Automatic Test Pattern Generation (ATPG): Process of automatically
generating test patterns that can be applied to the chip
■ Pattern generation happens on the gate-level netlist of the circuit
assuming a certain set of eventual defects/faults
 Fault Models: Abstraction of potential defects to ease the task of ATPG
■ E.g., stuck-at faults, transition faults
 Compression: Technology for reduced test data volume/test application
time. Compressed patterns are stored on the tester, while on-chip de-
compression logic ensures that uncompressed patterns can be applied.

* See [Agarwal00] for more information on basics/

advanced concepts in testing
Copyright Agarwal & Srivaths, 2007 Low-Power Design and Test, Lecture 8 8
 Outline

 Test Power Problem: Background and Basics

 Increasing Test Power Concerns
 Aspects of Test Power Dissipation
 DFT techniques targeting test power
 Power-aware ATPG
 Power Analysis Methodologies and Issues

Copyright Agarwal & Srivaths, 2007 Low-Power Design and Test, Lecture 8 9
 Increasing Test Power Concerns
 Test power is several times higher than normal mode power
■ Conflicting requirements of test time reduction practices
● Increasing test concurrency
 Test multiple modules simultaneously
● Increasing frequency of scan shift
■ Conflicting requirements of test data 12 Example circuit in 65nm technology
volume reduction practices 10 4.1X

Normalized
● Compression and compaction 8 3.5X

Power
techniques elevate circuit 6
switching 4

■ Tests are run at various stress 2

0
conditions (voltage and temperature)
Raw Compacted Compressed
■ Redundant switching in circuit logic Pattern type

during scan shift

Copyright Agarwal & Srivaths, 2007 Low-Power Design and Test, Lecture 8 10
 Increasing Test Power Concerns

 Peak test power can affect circuit yield

■ Example: Ti/Siemens 130nm ASIC design with 1M gates + 300kbits SRAM,
150 MHz clock frequency [Saxena-ITC03]
■ Some transition fault patterns passed only on or near 1.55V
■ Failure identified to be due to significant IR drop, caused by increased
switching in the launch to capture time window.
■ Example: Power supply voltage drops during scan shift operations
[Matsushita-ITC03]
200
 Test power is a determining (source: Intel)

Amperes
factor for packaging and 150

power grid design 100

 Power dissipation 50
constraints can also come 0
from a tester standpoint 0.25μm 0.18μm 0.13μm 0.09μm
■ Power availability during wafer Allowable current during test of unpackaged die
testing smaller [Intel-ITC04] Allowable current during normal o/p of packaged
chip

Copyright Agarwal & Srivaths, 2007 Low-Power Design and Test, Lecture 8 11
 Outline

 Test Power Problem: Background and Basics

 Increasing Test Power Concerns
 Aspects of Test Power Dissipation
 DFT techniques targeting test power
 Power-aware ATPG
 Power Analysis Methodologies and Issues

Copyright Agarwal & Srivaths, 2007 Low-Power Design and Test, Lecture 8 12
 Aspects of Test Power

 Average vs peak power

■ Average Power Dissipation = (Total Energy Consumed / Total time)
● Relevant for reliability issues – temperature effects, EM
■ Peak Power Dissipation
● Max power consumed in a cycle, Instantaneous peak power
● Tester implications, packaging implications for field test, IR drop issues can
have impact on power grid design

 Dynamic power vs Static power

■ Depends on the PTV corner
 At burn-in corner, static power can dominate with low frequency circuit
operation!
■ Leakage power implications
 An increasingly major component of static power, that is dependent on
the state of the circuit
■ Glitch power neglected
 Arise due to non-zero cell and interconnect delays, imbalance in logic
paths
■ As good as your power analysis flow!
Copyright Agarwal & Srivaths, 2007 Low-Power Design and Test, Lecture 8 13
 Aspects of Test Power

 Shift power versus Capture power

■ Low Frequency Shifts: Average Shift power may be a concern
■ High Frequency Shifts: Peak and Average power becomes a concern
■ Capture power: Fast capture pulses in transition patterns cause Peak power (IR drop) issues

 Structural Breakdown: Memories, Scan FF vs

Combinational logic
■ Memory power consumption can be dominant Seq comb
■ Must be aware of this while scheduling test of 100
multiple memories

PERCENTAGE
80
■ Scan FF vs Combinational logic

POWER
60
● 78% of the energy dissipated in the 40
combinational logic [Wunderlich99] 20
● 29%-53% of power dissipation seen in 0
combinational logic for industrial designs Ckt1 Ckt2 Ckt3 Ckt4

 Power Analysis Times and Logic Simulation Dump Sizes!

■ Ideally, you need the toggle activity in every test related cycle
■ Size of VCD dump file (for the TI/Siemens Design) to infer toggle activity in the launch-to-
capture time window is 2M !
Copyright Agarwal & Srivaths, 2007 Low-Power Design and Test, Lecture 8 14
 Outline

 Test Power Problem: Background and Basics

 Increasing Test Power Concerns
 Aspects of Test Power Dissipation
 DFT techniques targeting test power
 Power-aware ATPG
 Power Analysis Methodologies and Issues

Copyright Agarwal & Srivaths, 2007 Low-Power Design and Test, Lecture 8 15
 DFT for test power reduction (1) –Blocking Circuitry
 Basic Concept: Prevent switching in the comb. logic during shift
■ Use of blocking circuitry (NOR, MUX) at Q outputs connected
to combinational logic + Structured Tech
(minimal ATPG impact)
● Can manifest as part of special scan cells
- Normal Mode
■ Use of First Level Power Supply Gating [Bhunia05] Overheads
ScanEn

EN EN EN
ScanIn ScanOut
EN SD SQ SD SQ SD SQ

D Q D Q D Q

SD Scan Q
FF

D Q Q
SQ
Combinational Circuit

Enhanced Scan Cells

Usage in an Sequential Circuit
Copyright Agarwal & Srivaths, 2007 Low-Power Design and Test, Lecture 8 16
 First Level Power Supply Gating [Bhunia05]

(b) GND Gating with Floating output

(a) Simplest Version: GND Gating fixup

Copyright Agarwal & Srivaths, 2007 Low-Power Design and Test, Lecture 8 17
 DFT for test power reduction (2) – Scan Segmentation
[Whetsel-ITC00]

 Basic Concept: Divide a scan chain into multiple segments, and shift them one at at
time, while the other segments have their clocks gated.
■ Clock gating and by pass multiplexors added to provide acccess

SI1 CHAIN1, SEGMENT 1 CHAIN1, SEGMENT 2 SO1

SCAN OUTS
SCAN INS

SI2 CHAIN2, SEGMENT 1 CHAIN2, SEGMENT 2 SO2

SIn CHAINn, SEGMENT 1 CHAINn, SEGMENT 2 SOn

Gated_clk1 Gated_clk2

SEGMENT1 SEGMENT2

 + Does not add delay to the normal path

 + No significant change to ATPG
 + Test application time (TAT) impact negligible
 - Scan segment control implementation needed, routing implications
 - Delay test considerations (LOC ok)
Copyright Agarwal & Srivaths, 2007 Low-Power Design and Test, Lecture 8 18
 DFT for test power reduction (3) – Scan chain disable
[Sankaralingam02]

 Basic Concept: Operate one scan chain at a time (differs from scan segmentation
(how?)

 If a scan chain is disabled,

■ It is not clocked, scan chain does not shift/capture
 Issue: Deciding on the granularity of scan chain disabling
■ Inter-core (coarse-grained) versus Intra-core (fine-grained)

Copyright Agarwal & Srivaths, 2007 Low-Power Design and Test, Lecture 8 19
 Example: Scan Chain Disable in CELL processor
[IBM-ITC06]

 CELL Processor SPE

■ Each SPE has
● 150k latches
● 24 scan chains in LBIST
mode
■ Thold signal: When active, it
will stop the clock to the latch
element

Copyright Agarwal & Srivaths, 2007 Low-Power Design and Test, Lecture 8 20
 Something to think about ….

 Can you think of DFT options

that can help reduce test power?

 What trade-offs will you usually

worry about?

Copyright Agarwal & Srivaths, 2007 Low-Power Design and Test, Lecture 8 21
 Outline

 Test Power Problem: Background and Basics

 Increasing Test Power Concerns
 Aspects of Test Power Dissipation
 DFT techniques targeting test power
 Power-aware ATPG
 Power Analysis Methodologies and Issues

Copyright Agarwal & Srivaths, 2007 Low-Power Design and Test, Lecture 8 22
 Power-aware ATPG: Significance of Care Bits

[source: Butler-ITC04]
Fraction of care bits present

Fraction of care bits present

Percentage of Patterns ATPG pattern # (as APTG progresses)

 Test patterns consist of care bits and don’t care bits

■ E.g., a pattern (0XXX1XX) has 5 don’t care bits and 2 care bits
 The way the care bits are populated will affect ATPG quality and also have an impact on
power
■ For e. g., Random Fill (randomly filling care bits) may help in fortuitous detection of
faults, but at higher power consumption costs.

Copyright Agarwal & Srivaths, 2007 Low-Power Design and Test, Lecture 8 23
 Power-aware ATPG: Fill Techniques
 Different kinds of fill techniques can be used
■ Random fill: Fill in randomly
■ Zero fill: Fill in don’t care bits with ‘0’
■ One fill: Fill in don’t care bits with ‘1’
■ Adjacent fill: Fill in don’t care bits with the value of the nearest care bit. (Example:
0XXX1XX will be 0000111)
Module D: 600k gates, 8 scan chains, scan chain length 2970

Module M: 600k gates, 8 scan chains, scan chain length 3271

Fraction of cells switching in 3 of the Fraction of cells switching in 11 from

first 1000 patterns during launch-to-capture cycle all patterns during launch-to-capture cycle

 Fill adjacent performs better than other heuristics along various dimensions [Butler-
ITC04].

Copyright Agarwal & Srivaths, 2007 Low-Power Design and Test, Lecture 8 24
 Power-aware ATPG: Fill Techniques

 Earlier Example: IR drop issue with TI/Siemens ASIC

■ Transition pattern caused increased switching during launch-to-capture time
window
Source: [Saxena-ITC03]

Increasing No. of
0s placed
in “non-essential”
Scan cells

Copyright Agarwal & Srivaths, 2007 Low-Power Design and Test, Lecture 8 25
Inadequacy of Existing Low-Power ATPG Techniques
[Ravi-ICCAD07]
20 Variation of Power with fill techniques for compacted
patterns for an example module from a TI design
Random Fill 0-Fill
Dynamic Power

1-Fill Adj-Fill
15
(milliWatts)

12% Random Fill 0-Fill 1-fill Adj-Fill

10

0
First 5 patterns Last 5 patterns
Design A Design B
 Ineffectiveness of fill techniques for
10.7 325
compressed and compacted patterns

Power (mW)

Power (mW)
324

Design A
10.6

Design B
■ Compaction increases bit 0.9% 323
10.5
utilization in a pattern for testing 322
more faults 10.4
321
■ Compression reduces control 10.3 320
over don’t care bits due to 10.2 319
requirement for driving multiple Random Fill Adjacent Fill Zero Fill
scan chains Variation of Power with Fill Techniques
for Two Designs Supporting Compression

Copyright Agarwal & Srivaths, 2007 Low-Power Design and Test, Lecture 8 26
 Low Power ATPG Using Activity Threshold Controls
[Ravi-ICCAD07]
 Goals:
■ To come up with low power ATPG techniques which are better than fill
techniques
■ No modification to ATPG tool should be required
■ Benefit the generation of low power patterns even in compressed and
compacted scenarios
10
10
9 Random Fill
9

Number of Patterns
Random Fill 8
Number of Patterns

8 Adjacent Fill
7
Adjacent Fill 7

6 6 80% of Peak
5 5
4 Peak 4
3 Toggle 3
2 2
1 1
0 0
0.44 0.54 0.64 0.74 0.84 0.94 0.44 0.54 0.64 0.74 0.84 0.94
Normalized Toggles Normalized Toggles
Toggle Distribution using Reduced Activity Toggle Distribution
Fill Techniques for an Example for an Example Circuit Using the
Circuit Proposed Framework

Copyright Agarwal & Srivaths, 2007 Low-Power Design and Test, Lecture 8 27
 General Observations
SF1 adder tree
 Power constraints are simple
mathematical computations. SF2 +
transition

Example: Thresholded transition SF3 count

count for a scan out operation + +

<=
tc_out
+
SFN
τ
POWER CONSTRAINT CIRCUIT
 Power constraints can be
POWER
encapsulated as a circuit THRESHOLD
INPUTS
themselves (aka Power Constraint
Monitored
Circuits or PCC) Signals
Power
 Force ATPG tool to generate Constraint Target Circuit
Circuit
patterns on a circuit that includes
target circuit+PCC
Meet Constraint (Y/N)? OUTPUTS
[Constrained as Y for ATPG tool]
ENHANCED NETLIST FOR ATPG

Copyright Agarwal & Srivaths, 2007 Low-Power Design and Test, Lecture 8 28
 Low Power ATPG Methodology
 Exploits the capabilities of
the power constraint circuit Perform unconstrained
ATPG with

(PCC) to perform both

PCC logic no-faulted 3
Target
Circuit
pattern filtering and pattern Test
Patterns

generation Activity
Threshold Apply constraint checks Discarded
Generate Power Constraint using ATPG tool during violating
Circuit (PCC) using a partitioned fault simulation patterns
and LUT based architecture 4
1
List of
Monitored
Signals Good
PCC PCC I/O Patterns
Constraints

Identify faults not

detected by the good
Integrate with Target
patterns
Circuit 2 5

Perform constrained ATPG

to generate power-
Enhanced
constrained patterns
netlist 6

Power-
constrained
patterns

Copyright Agarwal & Srivaths, 2007 Low-Power Design and Test, Lecture 8 29
 Outline

 Test Power Problem: Background and Basics

 Increasing Test Power Concerns
 Aspects of Test Power Dissipation
 DFT techniques targeting test power
 Power-aware ATPG
 Power Analysis Methodologies and Issues

Copyright Agarwal & Srivaths, 2007 Low-Power Design and Test, Lecture 8 30
 Background: Status of Test Power Analysis
Flows
 Several power estimation
choices available for
functional use cases
 Gaps in test power Architecture
Yes
analysis flows Level
No
■ RTL option not RTL
(at present)
available yet
■ Architecture-level Gate-Level Yes
test power
calculators way off Power Estimation Accuracy Usability for
Estimation options Time Gap Test Power
 Current Status: Estimation
■ Gate-level power
estimators remain
the best bet.

Copyright Agarwal & Srivaths, 2007 Low-Power Design and Test, Lecture 8 31
Gate-level Test Power Estimation Flow (Conventional)
 Conventional flow adopted to Gate-Level Netlist
perform gate-level test power
estimation is simulation-based
■ Four main steps as shown in the Test Pattern
figure Generation
■ Step 3 (dump format conversion) Step 1
TDL
is optional
 For average test power consumption, Simulation
shift power due to a scanout
operation is calculated Step 2

■ The time interval of interest can

be specified as an input in Steps Dump Format
1/2/3 Conversion
 Estimation is performed at various Step 3
PVT corners
 Challenges for multi-million gate Gate-Level
SoCs: Power Estimator
■ Time-consuming Step 4
Power Report
■ Dump sizes can be very large
Copyright Agarwal & Srivaths, 2007 Low-Power Design and Test, Lecture 8 32
 Summary

 Test power consumption is a very important aspect of chip

design cycle
 Four facets of test power consumption
■ Test preparation/planning: Understanding the requirements
■ Power-aware DFT
■ Low-Power ATPG
■ Test Power Analysis
 What we did not cover today?
■ Test implications of power management circuitry

Copyright Agarwal & Srivaths, 2007 Low-Power Design and Test, Lecture 8 33
 References
 Books on Testing
■ [Agarwal00] Essentials of Electronic Testing for Digital, Memory and Mixed-Signal VLSI Circuits by Bushnell and
Agrawal, Springer, 2000

 Survey Papers/Articles
■ [Ravi-VDAT07] S. Ravi, “Addressing Test Power Issues in Digitial CMOS Design”, to appear in Proc. VLSI Design and Test
Symposium (VDAT), 2007.
■ [Ravi-ITC07] S. Ravi, “Power-aware Testing: Challenges and Solutions”, (invited lecture series), to appear in Proc.
International Test Conference (ITC), 2007.
■ [Jackson-07] T. Jackson, “Design-with-test for low-power devices”, EE Times-Asia, Jan 2007.
■ [Butler-ITC04] K. M. Butler, J. Saxena, T. Fryars, G. Hetherington, A. Jain, and J. Lewis, “Minimizing Power Consumption
in Scan Testing: Pattern Generation and DFT Techniques”, Proc. International Test Conference, pp. 355-364, 2004.

 DFT
■ [Wunderlich99] S. Gerstendorfer and H. –J Wunderlich, "Minimized power consumption for scan-based BIST," Proc.
International Test Conference, pp.77-84, 1999.
■ [Whetsel-ITC00] L. Whetsel, Adapting scan architectures for low power operation, Proc. International Test Conference,
pp. 863-872, 2000.
■ [IBM-ITC06] C. Zoellin, H. -J Wunderlich, N. Maeding and J. Leenstraa, “BIST Power Reduction Using Scan-Chain Disable
in the Cell Processor,” Proc. International Test Conference, 2006.
■ [Bhunia05] S. Bhunia, H. Mahmoodi, D. Ghosh, S. Mukhopadhyay, and K. Roy, “Low Power Scan Design Using First Level
Supply Gating”, IEEE Trans. onVLSI Systems, March 2005.
■ [Sankaralingam02] R. Sankaralingam and N. Touba, “Reducing Test Power During Test Using Programmable Scan Chain
Disable”, Proc. DELTA, pp. 159-166, 2002.
■ [Yoshida-ITC03]T. Yoshida and M. Watati, "A new approach for low-power scan testing," Proc. International Test
Conference, pp. 480- 487, 2003.
Copyright Agarwal & Srivaths, 2007 Low-Power Design and Test, Lecture 8 34
 References
 Low-Power ATPG
■ [Saxena-ITC03] J. Saxena et al, “A Case Study of IR-Drop in Structured At-Speed Testing”, Proc.
International Test Conference, pp. 1098-1104, 2003.
■ [Ravi-ICCAD07] S. Ravi, V. Devanathan, and R. Parekhji, “Methodology for Low Power Test Pattern
Generation Using Activity Threshold Control Logic”, to appear in Proc. International Conference on
Computer-Aided Design (ICCAD), 2007.

 Misc
■ [Intel-ITC04] S. Kundu, T. M. Mak, and R. Galivanche, "Trends in manufacturing test methods and their
implications," Proc. International Test Conference, pp. 679- 687, Oct. 2004.

Copyright Agarwal & Srivaths, 2007 Low-Power Design and Test, Lecture 8 35