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3 - CMOS Inverter

This document discusses the CMOS inverter, which is the simplest digital logic gate. It operates with low power loss and high speed. It has good noise margins in both low and high output states. The document describes the general properties of a digital logic gate, including small area for high packing density. It provides details on the DC analysis and voltage transfer characteristic of a CMOS inverter, explaining how the nMOS and pMOS transistors operate based on the input voltage. Key parameters like output high and low voltages, input high and low voltages, and noise margins are defined. Transient response is also briefly mentioned.

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188 views

3 - CMOS Inverter

This document discusses the CMOS inverter, which is the simplest digital logic gate. It operates with low power loss and high speed. It has good noise margins in both low and high output states. The document describes the general properties of a digital logic gate, including small area for high packing density. It provides details on the DC analysis and voltage transfer characteristic of a CMOS inverter, explaining how the nMOS and pMOS transistors operate based on the input voltage. Key parameters like output high and low voltages, input high and low voltages, and noise margins are defined. Transient response is also briefly mentioned.

Uploaded by

roxy8marie8chan
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as PPTX, PDF, TXT or read online on Scribd
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CMOS Inverter

COMPUTER ENGINEERING DEPARTMENT


ADAMSON UNIVERSITY
 The inverter is the simplest of all digital logic
gates. However, building an understanding of its
properties and operation is crucial for the design
and analysis of larger/ more complex logic gates.
 They operate with very little power loss and at
relatively high speed.
 Has good logic buffer characteristics, in that, its
noise margins in both low and high states are
large.
General Properties
 Small area is a desirable property for a digital logic gate
- Larger packing density
- Small parasitic capacitances
- Shorter interconnects
- Smaller chip area, hence higher number of devices per wafer
(lower cost)
 Fewer transistors for a logic gate usually results into
smaller area. Hence, minimum possible number of transistors
for a given gate is important.
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CMOS Inverter DC Analysis


CMOS Inverter DC Analysis

• DC Analysis of CMOS Inverter


– Vin, input voltage
– Vout, output voltage
– single power supply, VDD
– ground reference
– find Vout = f(Vin)

• Voltage Transfer Characteristic (VTC)


– plot of Vout as a function of Vin
– vary Vin from 0 to VDD
– find Vout at each value of Vin
CMOS Inverter DC Analysis
Transistors Operation Region
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NMOS and PMOS Operations


NMOS
PMOS
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CMOS Inverter VTC


• Output High Voltage, VOH (maximum output voltage)
 occurs when input is low (Vin = 0V)
 pMOS is ON, nMOS is OFF
 pMOS pulls Vout to VDD
 VOH = VDD

• Output Low Voltage, VOL (minimum output voltage)


 occurs when input is high (Vin = VDD)
 pMOS is OFF, nMOS is ON
 nMOS pulls Vout to Ground
 VOL = 0 V
Gate Voltage, f(Vin)
VGSN=Vin
VSGP=VDD-Vin

Drain Voltage, f(Vout)


VDSN=Vout
VSDP=VDD-Vout
Transition Region (between VOH and VOL )
Input Low Voltage, VIL
– Vin such that Vin < VIL = logic 0
– point ‘a’ on the plot
• where slope,

Input High Voltage, VIH


– Vin such that Vin > VIH = logic 1
– point ‘b’ on the plot
• where slope =-1
Voltage Noise Margins
– measure of how stable inputs are with respect to signal
interference
– VNMH = VOH - VIH = VDD - VIH
– VNML = VIL - VOL = VIL
– desire large VNM H and VNM L for best noise immunity
point on VTC where Vout = Vin
also called midpoint voltage, VM
Vin = Vout = VM
- exactly in the middle

- noise margin is good


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Transient Response
REFERENCES:

Digital Integrated Circuits— A Design Perspective, Jan


M. Rabaey, Anantha Chandrakasan, and Borivoje Nikolic

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