EE204

Computer Architecture

Lecture 17- Multicycle Processor

Datapath
3rd March, 2011

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 Multicycle Datapath

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 MultiCycle Datapath & Control Signals

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 One Single ALU
 One single ALU is used to perform all of
the necessary functions:
 An arithmetic operation on two
register operands
 Add a register to a sign-extended
constant, for computing memory
addresses in lw/sw instructions
 Compute PC+4 to increment the PC
 Add a sign-extended, shifted offset to
(PC+4) for branches
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 Implications of Shared Functional
Units
 Need to add multiplexors or expand
existing multiplexors

 e.g. Memory unit now contains both

instructions (address in PC) and data
(address in ALUOut)

 e.g. ALU now must accommodate all

inputs from previous ALU and adders.

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 Two extra multiplexers
 To enable all the actions listed for the ALU,
two extra multiplexers are needed
 A 2-to-1 mux, ALUsrcA, selects whether the
first ALU input is the PC or a register
 A 4-to-1 mux, ALUSrcB, selects the 2nd
input from among
 the register file
 a constant 4
 a sign-extended constant, and
 a sign-extended and shifted constant

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 One single memory

 One single memory is used in both the

instruction fetch and data access stages.
 The address for this memory may come from:
 the PC register, when fetching an instruction
 the ALU output, when doing a lw/sw
instruction and need the effective memory
address.
 => add a 2-to-1 mux, IorD, to select whether
the memory is being accessed for instructions
or for data.
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 Breaking Instruction into Clock
Cycles
 Goal: balance the amount of work done in each
cycle so that we can minimize clock period.
 Restrict each step to contain at most 1 of
 ALU operation
 Register File Access
 Memory Access
 Clock cycle time will be longest of above operations.

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 Complete Multicycle Datapath

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 Arithmetic Instruction Steps
 Instruction Fetch
 IR = Mem[PC]
 PC = PC + 4
 Instruction Decode
 A = Reg[IR[25-21]]
 B = Reg[IR[20-16]]
 Instruction Execution
 ALUOut = A op B
 Store Result
 Reg[IR[15-11]] = ALUOut

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 lw Instruction Steps
 Instruction Fetch
 IR = Mem[PC]
 PC = PC + 4
 Instruction Decode
 A = Reg[IR[25-21]]
 Address calculate
 ALUOut = A + sign-extd. (IR[15 – 0])
 Memory Access
 MDR = Mem[ALUOut]
 Memory read completion
 Reg[IR[20-16]] = MDR

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 sw Instruction Steps
 Instruction Fetch
 IR = Mem[PC]
 PC = PC + 4
 Instruction Decode
 A = Reg[IR[25-21]]
 B = Reg[IR[20-16]]
 Address calculate
 ALUOut = A + sign-extd. (IR[15 – 0])
 Memory write completion
 Mem[ALUOut] = B

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 Branch Instruction Steps
 Instruction Fetch
 IR = Mem[PC]
 PC = PC + 4
 Instruction Decode
 A = Reg[IR[25-21]]
 B = Reg[IR[20-16]]
 ALUOut = PC + (sign-extd.(IR[15-0]) << 2)
 Branch Execution
 If (A == B) PC = ALUOut

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 Jump Instruction
 Instruction Fetch
 IR = Mem[PC]
 PC = PC + 4
 Jump Execution
 PC = PC[31-28] || (IR[25-0] <<2)

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 Breaking instruction into steps
 Instruction Fetch
 IR = Mem[PC] all instructions
 PC = PC + 4 all instructions
 Instruction Decode
 A = Reg[IR[25-21]] all inst. except jump
 B = Reg[IR[20-16]] arith. & branch
 ALUOut = PC + (sign-extd.(IR[15-0]) << 2)
branch inst. only

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 Breaking instruction into steps
 Execution, Mem. Address calc. or branch
 ALUOut = A + sign-extd. (IR[15 – 0]) lw/sw
inst.
 ALUOut = A op B arith.
inst.
 If (A == B) PC = ALUOut branch
inst.
 PC = PC[31-28] || (IR[25-0] <<2) jump
inst.
 Memory Access or R-type Inst. Completion
 MDR = Memory[ALUOut] lw inst.
 Mem[ALUOut] = B sw inst.
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 Reg[IR[15-11]] = ALUOut arith.
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 Break Instruction into steps
 Memory read completion
 Reg[IR[20-16]] = MDR lw inst.

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 Finite State Machine Control

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Instruction Fetch
Cycle 1 All instructions
26 Sh. 28
Left 32
PCSource

PCWrite 1 x 2 Concat. 0
4
PCWriteCond 2
Control
Zero ALUOp 0 0

IorD Inst[25-0] [31-28]

0 MemRead
Inst[31-26] 1

1 1 x x 0
MemWrite 0 IRWrite MemToReg RegDest RegWrite ALUSelA
PC
or 0
PC PC+4
0 [25-21] 0
Read address Read reg num A
1
Memory
[20-16] Read reg data A A 1
Read reg num B Zero
Instr. [31-0] ALU
Read data ALUSelB
Write address
Registers Result Out
Instr. Reg 0
1
[15-11] Write reg num
Read reg data B B 0
Write data 1
Write reg data 4 1

IorD=0 MDR 1
2

MemRead=1 3

MemWrite=0 ALUOp=0 0
Sh.
IRWrite=1 PCWrite=1 16 sign 32
Left
[15-0] extend ALU
ALUSelA=0 PCSource=0 2 control
[5-0]
ALUSelB=1 RegWrite=0

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Instr. Decode/Reg. Cycle 2 All instructions
26 Sh. 28
Left 32
PCSource

Fetch
0 0 PCWrite 2 Concat. x
4
PCWriteCond 2
Control
Zero ALUOp 0 0

x IorD 0 Inst[31-26] Inst[25-0] [31-28] 1

MemRead
0 x x 0
MemWrite 0 IRWrite MemToReg RegDest RegWrite ALUSelA
PC
or 0
PC PC+4
0 [25-21] 0
Read address Read reg num A
1
Memory
[20-16] Read reg data A A 1
Read reg num B Zero
Instr. [31-0] ALU
Read data ALUSelB
Write address
Registers Result Out
Instr. Reg 0
3
[15-11] Write reg num
Read reg data B B 0
Write data 1
Write reg data 4 1
2
MDR 1
MemRead=0 3
MemWrite=0 ALUOp=0 0
Sh.
IRWrite=0 PCWrite=0 16 sign 32
Left
[15-0] extend ALU
ALUSelA=0 PCWriteCond=0 2 control
ALUSelB=3 RegWrite=0 [5-0]

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 Fetch & Decode Instruction State
Diagram

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