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Lec 7

This document summarizes a lecture on computer architecture and memory addressing. It discusses: 1. Address decoding and memory addressing using a 2732 EPROM chip as an example. It explains how the address lines are used to select memory registers and assert the chip enable. 2. Interfacing the 8155 chip with the 8085 microprocessor. The 8155 has 256 bytes of RAM, I/O ports and a timer. It generates internal control signals and demultiplexes the address/data lines to interface directly with the 8085. 3. Memory interfacing and addressing schemes for the 8155 chip. It allows memory fold back by leaving some address lines unconnected so multiple addresses can access the

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33 views

Lec 7

This document summarizes a lecture on computer architecture and memory addressing. It discusses: 1. Address decoding and memory addressing using a 2732 EPROM chip as an example. It explains how the address lines are used to select memory registers and assert the chip enable. 2. Interfacing the 8155 chip with the 8085 microprocessor. The 8155 has 256 bytes of RAM, I/O ports and a timer. It generates internal control signals and demultiplexes the address/data lines to interface directly with the 8085. 3. Memory interfacing and addressing schemes for the 8155 chip. It allows memory fold back by leaving some address lines unconnected so multiple addresses can access the

Uploaded by

ilyaas123
Copyright
© © All Rights Reserved
Available Formats
Download as PPT, PDF, TXT or read online on Scribd
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Computer Architecture

Lecture 7

by

Engineer A. Lecturer Aymen Hasan AlAwady

8/12/2013

University of Kufa - Informatics Center for Research and Rehabilitation 1

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1. Addressing decoding and
memory addresses
Review Example: Analyze the possible logic levels of
the memory chip (2732 EPROM).

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1. Addressing decoding and
memory addresses
• We have 16 address lines.
• A12 – A15 must be 000 to assert chip enable.
• A0 – A11 can assume any combination from all 0s to all 1s.
(we have 4096 registers, so we need 12 address)
• A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
0000 H 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0 F F F
0FFF H 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1
Chip Enable Register Select
1.For registers selection, we have 4096 register, so we need 12 address
lines (212 ) from 0000 H to 0FFF H.
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2. For chip select we need 0H to 0H, since the output line on O0.
Reading signal

4
Homework: Analyze the possible logic levels of the
memory chip 6116 Memory and draw the address
decoding and writing from memory through the interfacing
with 8085 MPU

5
2. Case study: Interfacing the
8155
• The 8155 is a special chip designed by Intel to
work with the 8085 to demonstrate the
interfacing of the 8085 MPU.
• The 8155 has 256 bytes of RAM, 2
programmable I/O ports and a timer.
• It is usually used in systems designed for use in
university labs.

• We will now concentrate on the memory part of


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the 8155.
Modified Lecture by Dr. Bassel Soudan
2. 1 Interfacing the 8155 memory
section
• The 8155 contains all the circuitry needed to interface to the
8085 directly.
• It has 8 lines that match the AD0-AD7 of the 8085 and
one CE (chip enable).
• It has 5 control lines that match the control and status
lines of the 8085.
• The address/data lines are demultiplexed internally inside
the 8155 and the control signals needed for the memory
are also generated internally.

• All that is needed to interface the 8155 to the 8085 is logic


to control the 8155 to determine the starting address of 7
the memory segment.
Modified Lecture by Dr. Bassel Soudan
2. 1 Interfacing the 8155 memory
section
It is possible in a small computer system to use multiple
addresses for the same memory location.
• In that case, memory is small and limited, so it doesn’t
make sense to use all of the address lines to specify each
of the locations.
• Some of the address lines are left unconnected.
• That results in don’t care address lines.
• The result will be that the same set of memory registers
is used when the user enters the different addresses.
• This process is called memory fold back. i.e. the new
address range is folded back over the old address.
• Again, this allows the use of a much simpler decoding 8
circuit for the address lines.
Modified Lecture by Dr. Bassel Soudan
2.2 Memory interfacing in
8155
A15

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2.2 Memory interfacing in
8155
A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
2100 H 0 0 1 0 0 0 0 1 0 0 0 0 0 0 0 0

21FF H
0 0 1 0 0 0 0 1 1 1 1 1 1 1 1 1
Chip Enable Don’t care Register Select
• A8, A9 and A10 are don care lines, means they could be 0s or
1s (don’t care).
• When they are all 0s the starting range will be 2000 H – 20FF
H and when only A8 be 1 the address will be 2100 H – 21FF H
and when all of they be 1s, the address will be 2700 H – 27FF
H.
• All of the above addresses are pointed at the same memory 10
registers (memory fold back).
3. Testing Memory Interfacing
Circuits
• Testing a memory chip in an existing system is as easy as
loading a byte at a specific address and then verifying
that it was loaded.

• A few more addresses should also be checked.

• In case of fold back memory, one should test the


different address ranges for the don’t care address lines.
• In fact, in 8155 the memory fold back space is in range
(2100 H – 27FF H) which is cant be used.
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Modified Lecture by Dr. Bassel Soudan


End of lecture 7

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