SUMMAR TRAINING

ON

VHDL PROGRAMMING
 1.INTRODUCTION
• VHDL is a hardware description language
• Describe behavior of an electronic ckt or system,from
which the physical circuit can be implemented
• VHDL stands for Very High Speed Integrated Cricuit
(VHSIC) Hardware Description Language(VHDL)
• Funded by DOD
• First version in 1980 ie VHDL 87
• Upgraded to VHDL 93
• First hardware description language to be
standardized by IEEE through 1076
• Upgraded to IEEE 1164
Introduction Cont…

• Intended for ckt synthesis and simulation

• Though VHDL is fully simulatable,not all construct are synthesizable
• Basic reason for using VHDL(or its competitor,Verilog) is standard technology/vendor
independent language, and is therefore portable and reusable

----xxx----

Next APPLICATION
 APPLICATIONS
• Programmable Logic Devices(CPLDs,FPGAs)
• ASIC(Application Specific Integrated Ckt)
Once a VHDL code has been writtean,it can be used either to
implement the ckt on
1. Programmable logic Devices from Altera,Xilinx Atmel
etc
2. Can be submitted to a foundry for fabrication of an ASIC
chip
Currently many complex commercial chips (microcontrollers,
for example) are designed using such an approach
 FINAL NOTE
• VHDL statements are inherently concurrent
(parallel)
• For this reason VHDL is usually referred to
as a code rather than a program
• In VHDL only statements placed inside a
PROCESS,FUNCTION or PROCEDURE
are executed sequentially
 DESIGN FLOW
VHDL entry
(RTL Level)

Compilation

Netlist
(Gate Level)

Synthesis Optimization

Optimized netlist
(Gate Level) Simulation
Place and Route

Physical Device
Simulation
DESIGN FLOW Cont . . .

Start Design by writing VHDL code (.vhd extension)

Synthesis process starts with compilation of .vhd code
Describe ckt at Register Transfer Level(RTL)
RTL into a netlist at the gate level
Now optimization is performed on the gate-level net-list for speed
or for area
At this stage design can be simulated
Finally, a Place and Route (filter) software will generate the
physical layout for a PLD/FPGA chip or will generate the masks
for an ASIC
 EDA(Electronic Design Automation) TOOLS

• Some tools (place and route for example) are offered

as part of a vendor’s design suit e.g. Altera’s Quartus
II, which allows the synthesis of VHDL code onto
Altera’s CPLD/FPGA chips,or Xilinx’s ISE suite,for
Xilinx CPLD/FPGA chips)
• Mentor Graphics,Synopsis,Synplicity ModelSim are
some other vendors dealing with specialized EDA
tools at different level
 TRANSLATION OF VHDL INTO CKT CODE

A A B Cin S Cout
S 0 0 0 0 0
B Full 0 0 1 1 0
Adder Cout 0 1 0 1 0

cin 0 1 1 0 1
1 0 0 1 0
1 0 1 0 1
1 1 0 0 1
1 1 1 1 1

NOTE:-
1. S must be high when ever the number of inputs that are
high is odd
2. While Cout must be high when two or more inputs are high
VHDL CODE
library ieee; As can be seen it consist of an
use ieee.std_logic_1164.all; ENTITY,which is a
entity full_adder is description of the
port (a,b,cin:in bit; pins(PORTS) of the ckt and
s,cout:out bit); an ARCHITECTURE,which
end full_adder; describes how the circuit
------------------------------------- should function.Sum bit is
architecture dataflow of full_adder is computed as a b cin,
begin while cout is obtained from
s <= a xor b xor cin; cout = a.b + a.cin + b.cin
cout<= (a and b) or (a and cin) or (b and
cin);
A
end dataflow;
S
B Full
Adder Cout
CIRCUIT cin
 OUTPUT VARIABLE OUTPUT VALUE

OUTPUT WAVEFORM

INPUT VALUE
INPUT VARIABLE

SIMULATION RESULT
2.CODE STRUCTURE
 CODE STRUCTURE

Contains a list of all libraries to be LIBRARY

used in design for example ieee, std, Declarations
work,etc

BASIC VHDL CODE

Specifies the I/O pins of the circuits ENTITY

Contains the VHDL code,which

describe how the circuit should ARCHITECTURE
behave (function)
 LIBRARY DECLARATION
SYNTAX
LIBRARY library_name;
USE library_name.package_name.package_parts;
EXAMPLE-1
LIBRARY ieee; --A semi-colon(;) indicates the end of line
USE ieee.std_logic_1164.all; --double dash denotes comments

FUNDAMENTAL PARTS OF A LIBRARY

LIBRARY
PACKAGE

FUNCTIONS
PROCEDURES
COMPONENTS
CONSTANTS
TYPES
 LIBRARY BY DEFAULT ADDED

EXPLICITY WRITTEN

IEEE STANDARD WORK

PACKAGE PACKAGE PACKAGE

ieee.std_logic_1164.all std.standard.all work.all

 EXAMPLE-2
LIBRARY std;
USE std.standard.all;
EXAMPLE-3
LIBRARY work;
USE work.all;

ieee.std_logic_1164:- Specified multi level logic system i.e.

STD_LOGIC(8 levels) and STD_ULOGIC(9 levels)

std.standard.all:- Specified resource library (data types,text i/o,etc) for

VHDL design environment

Work.all:- where we save our design (the .vhd file,plus all files created
by the compiler,simulator etc)

ALL THESE LIBRARIES WILL BE FURTHER DESCRIBED AND USED

 ENTITY
SPECIFICATIONS OF ALL INPUT AND OUTPUT PINS(PORTS)
OF THE CIRCUIT

SYNTAX
ENTITY entity_name is
PORT (
port name : signal_mode signal_type;
port name : signal_mode signal_type;
. . . );
END entity_name;
 SIGNAL_MODE
IN OUT
OUT CKT INOUT
IN
INOUT BUFFER
BUFFER

•IN AND OUT are truly unidirectional pins

•INOUT is a bi-directional pins

•BUFFER on the under hand is employed when the output signal must
be used internally
 SIGNAL_TYPE
BIT
STD_LOGIC
INTEGER
•DATA TYPES WILL BE DISCUSSED IN DETAIL IN COMING
CHAPTERS
 EXAMPLE : - Let us consider the NAND gate of below. Its
ENTITY can be specified as :

ENTITY nand_gate IS
a
PORT (a,b:IN BIT; x
b
x: OUT BIT);
END nand_gate;

The meaning of the ENTITY above is the following:

•The circuit has three I/O pins i.e. two inputs(a and b) and one output(x)
•All three signals are type BIT.
•The name chosen for the entity was nand_gate
 ARCHITECTURE
It is a description of how the circuit should behave (function)

SYNTAX
ARCHITECTURE architecture_name OF
entity_name IS
[declaration] Part 1 optional signals and
constant are declared
BEGIN
(code) Part 2 VHDL programe code

END architecture_name;

Like in the case of an entity,the name of an architecture

Can be anything except VHDL reserved words
 a
EXAMPLE : - Let us consider the NAND gate. x
b
ARCHITECTURE myarch OF nand_gate IS
BEGIN
X <= a NAND b;
END myarch;
The meaning of the ARCHITECTURE above is

•Ckt must perform NAND operation between two inputs

signals (a,b) and assign (“<=”) the result to the output pin (x)
•The name chosen for this architecture was myarch
•In this example there is no declarative part and the code
contains just a single assignment
ARCHITECTURE MODELING STYLE

STRUCTURE MODELING

DATA FLOW MODELING

BEHAVIOR MODELING

MIXED MODELING
 1.STRUCTURE MODELING
SET OF INTERCONNECTED COMPONENTS

A X1 SUM ARCHITECTURE ha_structure of half_adder is

COMPONENT xor2
B A1 CARRY
A HALF ADDER CKT PORT (x,y: IN BIT; z:OUT BIT);
END COMPONENT;
COMPONENT and2
PORT (l,m:IN BIT;n:OUT BIT);
END COMPONENT;
BEGIN
x1:xor2 PORT MAP (a,b,sum);
a1:and2 PORT MAP (a,b,carry);
END ha_structure
 2.DATA FLOW MODELING
AS A SET OF CONCURRENT ASSIGNMENT STATEMENTS TO REPRESENT
DATA FLOW

A X1 SUM ARCHITECTURE ha_concurrent of half_adder is

BEGIN
B A1 CARRY
A HALF ADDER CKT sum <=a XOR b
carry <=a AND b
END ha_concurrent ;
 3.BEHAVIORAL MODELING

A SET OF SEQUENTIAL ASSIGNMENT STATEMENTS TO REPRESEN

BEHAVIOR

A X1 SUM ARCHITECTURE ha_behavioral of half_adder is

BEGIN
B A1 CARRY
A HALF ADDER CKT PROCESS (a,b)
VARIABLE sum,carry:BIT;
BEGIN
Sum <= a xor b;
carry <= a AND b
END PROCESS;
END ha_behavioral ;

4.MIXED MODELING
COMBINATION OF THE ABOVE THREE
d q EXAMPLE-1
DFF Fig shows DFF triggered at the rising edge
clk of the clk and with an asynchronous reset
Input rst.When rst=1,the output must be turned
Low,regardless of clk.Otherwise,the output
Must copy the input i.e q <= d at the moment
rst when clk changes from 0 to 1
1-----------------------------------------------------------------------
2 LIBRARY ieee;
3 USE ieee.std_logic_1164.all;
4------------------------------------------------------------------------
5 ENTITY dff IS
6 PORT (d,clk,rst:IN STD_LOGIC;
7 q:OUT STD_LOGIC);
8 END dff;
9------------------------------------------------------------------------
10 ARCHITECTURE behavior OF dff is
11 BEGIN
12 PROCESS (rst,clk)
13 BEGIN
14 IF (rst=‘1’) THEN
15 Q <= ‘0’;
16 ELSIF (clk’EVENT AND clk=‘1’) THEN
17 Q <= d;
18 END IF;
19 END PROCESS;
20 END behavior;
21 -----------------------------------------------------
 EXPLANATION
LINE 2-3: Library declaration (Library name and Library use
clause).Recall that the other two indispensable libraries (std and work)
are made visible by default.
LINE 5-8: Entity dff
LINE 10-20: Architecture behavior
LINE 6: Input ports(input mode can only be IN).In this example,all input
signal is of type STD_LOGIC.
LINE 7: Output port(output mode can be OUT,INOUT,or BUFFER).Here
the output is also of type STD_LOGIC
LINE 11-19: Code part of the Architecture (from word BEGIN on)
LINE 12-19: A PROCESS (inside it the code is executed sequentially)
 EXPLANATION
LINE 12: The PROCESS is executed every time a signal
declared in its sensitivity list changes.In this example
every time rst or clk changes the PROCESS is run..
LINE 14-15: Every time rst goes to ‘1’ the output is
reset,regardless of the clk (asyn reset)
LINE 16-17: If rst is not active,plus clk has changed (an
EVENT occurred on clk),plus such event was a
rising edge (clk=‘1’),then the input signal (d) is
stored in the FF (q <= d)
LINE 15 and 17: The “<=“ is used to assign a value to a
SIGNAL,”:=“would be used for a VARIABLE.All ports in
an entity are signals by default
LINE 1,4,9,21: Commented
Note:-VHDL is not case sensitive
 3.DATA TYPES
PRE-DEFINED DATA TYPES
USER-DEFINED DATA TYPES
SUBTYPES
ARRAYS
PORT ARRAYS
RECORDS
SIGNED AND UNSIGNED DATA TYPES
DATA CONVERSION
 INTRODUCTION
• ESSENTIAL TO KNOW DATA TYPES
FOR EFFICIENT VHDL CODING
• WHAT DATA TYPES ARE ALLOWED
• HOW TO SPECIFY AND USE THEM
• ALL FUNDAMENTL DATA TYPES ARE
DESCRIBED HERE
• DATA COMPATIBILITY AND DATA
CONVERSION
 PRE-DEFINED DATA TYPES
• CONTAINS A SERIES OF PRE-DEFINED DATA TYPES
• SPECIFIED BY ieee 1076 AND ieee 1064
• SUCH DATA TYPES DEFINITIONS CAN BE FOUND IN
FOLLOWING PACKAGES AND LIBRARIES AS SHOWN
BELOW

1. LIBRARY
(std)

PACKAGE
(standard)

DEFINITIONS
(BIT,BOOLEAN,INTEGER AND REAL)
2. LIBRARY
(ieee)

PACKAGE
(std_logic_1164)

DEFINITIONS
(STD_LOGIC AND STD_ULOGIC)
3. LIBRARY
(ieee)

PACKAGE
(std_logic_arith)

DEFINITIONS
SIGNED AND UNSIGNED
conv_integer(p),conv_unsigned(p.b),conv_signed(p,b)
and conv_std_logic_vector(p,b)
 4. LIBRARY
(ieee)

PACKAGE
(std_logic_signed and std_logic_unsigned)

Contains functions that allow operations

With STD_LOGIC_VECTOR data to be
Performed as if the data were of types SIGNED or
UNSIGNED

ALL PRE-DEFINED DATA TYPES (SPECIFIED IN PACKAGES AND

LIBRARIES LISTED ABOVE )ARE DESCRIBED ON NEXT SLIDE
 BIT AND BIT_VECTOR
•MEANS TWO LEVEL LOGIC (‘0’,’1’)

EXAMPLE 1.
SIGNAL x : BIT;
--x is declared as a one-digit signal of type BIT

EXAMPLE 2.
SIGNAL y : BIT_VECTOR (3 DOWNTO 0);
--y is a 4-bit vector,with the lefmost bit being the MSB

EXAMPLE 3.
SIGNAL w : BIT_VECTOR(0 TO 7);
--w is 8-bit vector, with the rightmost bit being the MSB

Based on the above ,following assignments would be legal (to

assign a value to a signal the “<=“operator must be used):
FOR EXAMPLE 1.
x <= ‘1’;
--x is a single bit signal whose value is ‘1’.Notice that single (‘’)
----are used for single bit.

EXAMPLE 2.
y <= “0111”;
--y is a 4-bit signal,whose value is “0111” MSB=‘0’.Notice that
double quote (“ ”) are used for vectors

EXAMPLE 3.
w <= “01110001”;
--w is 8-bit signal, whose value is “01110001” (MSB=‘1’)

Based on the above ,following assignments would be legal (to

assign a value to a signal the “<=“operator must be used):
STD_LOGIC AND STD_LOGIC_VECTOR
8-VALUED LOGIC SYSTEM INTRODUCED IN THE IEEE
1164 STANDARD

S.NO. VALUE MEANING

1. ‘X’ Forcing unknown
2. ‘0’ Forcing low
3. ‘1’ Forcing high
4. ‘Z’ High impedance
5. ‘W’ Weak unknown
6. ‘L’ Weak low
7. ‘H’ Weak High
8. ‘-’ Don’t Care
EXAMPLE 1.
SIGNAL x : STD_LOGIC;
--x is declared as a one-digit scalar signal of type STD_LOGIC

EXAMPLE 2.
SIGNAL y : STD_LOGIC_VECTOR (3 DOWNTO 0) := “0001”;
--y is a 4-bit vector,with the lefmost bit being the MSB.The initial
value (optional) of y is “0001”.Notice that the “:=“ operator is
used to establish the initial value
•STD_LOGIC LEVELS ARE INTENDED FOR SIMULATION
•‘0’,’1’,’Z’ ARE SYNTHESIZABLE WITH NO RESTRICTIONS
•WITH RESPECT TO WEAK VALUE S THEY ARE RESOLVED IN
FAVOUR OF THE FORCING VALUES IN MULTIPLY DRIVEN
NODE(AS SHOWN INTABLE)
•IF ANY TWO STD_LOGIC ARE CONNECTED TO THE SAME
NODE,THEN CONFLICTING LOGIC LEVELS ARE
AUTOMATICALLY RESOLVED ACCORDING TO THE TABLE
RESOLVED LOGIC SYSTEM (STD_LOGIC)

X 0 1 Z W L H -
X X X X X X X X X
0 X 0 X 0 0 0 0 X
1 X X 1 1 1 1 1 X
Z X 0 1 Z W L H X
W X 0 1 W W W W X
L X 0 1 L W L W X
H X 0 1 H W W H X
- X X X X X X X X
 STD_ULOGIC_VECTOR
9-VALUED LOGIC SYSTEM INTRODUCED IN THE IEEE
1164 STANDARD
S.NO. VALUE MEANING
1 U UNRESOLVED
2. ‘X’ Forcing unknown
3. ‘0’ Forcing low
4. ‘1’ Forcing high
5. ‘Z’ High impedance
6. ‘W’ Weak unknown
7. ‘L’ Weak low
8. ‘H’ Weak High
9 ‘-’ Don’t Care
BOOLEAN : True,False
INTEGER : 32-bit integers (from –2,147,483,647 to 2,147,483,647)
NATURRAL : Non-negative integers (from 0 to 2,147,483,647)
REAL : Real numbers ranging from –1.0E38 to 1.0E38.Not
synthesizable

Physical literals are used to inform physical quantities,like time,voltage

etc.Useful in simulation. Not synthesizable

Character literals are single ASCII character or a string of such

characters.Not synthesizable.

EAMPLES :
x0 <= ‘0’; --bit,std_logic,std_ulogic value ‘0’
x1 <= “00011111”; --bit_vector,std_logic_vector,std_ulogic_vector,signed,or
--unsigned
x2<= “0001_1111”;--underscore allowed to ease visualization
x3 <= “101111” –binary representation of decimal 47
x4 <= B”101111” --binary representation of decimal 47
x5 <= O”57” --octal representation of decimal 47
x6 <= X”2F” --hexadecimal representation of decimal 47
n <= 1200; –integer
m <= 1_200; --integer,underscore allowed
IF ready THEN . . . --Boolean,executed if ready=true
y <= 1.2E-5; --real, not synthesizable
q <= d after 10 ns; --physical,not synthesizable
 LEGAL AND ILLEGAL OPERATIONS BETWEEN DATA OF DIFFERENT
TYPES
SIGNAL a: BIT;
SIGNAL b: BIT_VECTOR (7 DOWNT 0 );
SIGNAL c:STD_LOGIC;
SIGNAL d:STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL e:INTEGER RANGE 0 to 255;
a <= b(5); --legal same scalar type:BIT
--------------------------------------------------------------------------------------
b(0) <= a; --legal same scalar type:BIT

c <= d(5); --legal (same scalar type:STD_LOGIC)

d(0) <= c; --legal (same scalar type:STD_LOGIC)

a <= c; --illegal (type mismatch:BIT x STD_LOGIC)
b <= d; --illegal (type mismatch:BIT_VECTOR x STD_LOGIC)
e <= b; --illegal (type mismatch:INTEGER x BIT_VECTOR)

e <= d; --illegal (type mismatch:INTEGER x STD_LOGIC_VECTOR)

 USER DEFINED DATA TYPES
VHDL ALLOWS THE USER TO DEFINE HIS/HER OWN DATA TYPES
These are classified in INTEGER and ENUMERATED
USER DEFINED INTEGER TYPES
TYPE integer IS RANGE –2147483647 TO +2147483647;
--This is indeed the pre-defined type INTEGER.

TYPE natural IS RANGE 0 TO +2147483647;

--This is indeed the pre-defined type NATURAL.

TYPE natural IS RANGE -32 TO +32;

--A user defined subset of integers.

TYPE student_grade IS RANGE 0 TO +100;

--A user defined subset of integers or naturals
 USER DEFINED ENUMERATED
TYPES
TYPE bit IS (‘0’,’1’);
--This is indeed the pre-defined type BIT.
TYPE my_logic IS (‘0’,’1’,’Z’);
--A user defined subset of std_logic
TYPE bit_vector IS ARRAY (NATURAL RANGE <>) OF BIT;
--This is indeed the pre-defined type BIT.
--RANGE <> IS used to indicate that the range is unconstrained
--NATURAL RANGE <>, on the other hand, indicates that the only
--restriction is that the range must fall within NATIURAL RANGE
TYPE state IS (idle,forward,backward,stop);
--An enumerated data type,typical of finite state machines.
TYPE color IS (red,green,blue,white);
--Another enumerated data type.
 NOTE :- The encoding of the enumerated type is done sequentially
Automatically.Unless specified otherwise by a user-defined attribute
discussed later For example,for the type color above,two bits are
necessary.TYPE declarations are not allowed in ENTITY.
SUBTYPES
The main reason for using a subtype rather than specifying a new
type is that,though operations between different types are not
allowed,they are allowed between a subtype and its corresponding
base type.
Example: The subtype below were derived from the types
presented in the previous examples.

SUBTYPE my_logic IS STD_LOGIC RANGE ‘0’ TO ‘Z’;

--Recall that STD_LOGIC=(‘X’,’0’,’1’,’Z’,’W’,’L’,’H’,’-’)
--Therefore my_logic=(‘0’,’1’,’Z’)

SUBTYPE my_color IS Color RANGE red TO blue;

--Since color=(red,green,blue,white),then
 SUBTYPE small_integer IS INTEGER RANGE -32 TO 32;
--A subtype of INTEGER

EXAMPLE : Legal and illegal operations between

types and subtypes
SUBTYPE my_logic IS STD_LOGIC RANGE ‘0’ TO ‘1’;
SIGNAL a:BIT;
SIGNAL b:STD_LOGIC;
SIGNAL c:my_logic;
------------------------------------------------------------
b <= a; --illegal (type mismatch: BIT Vs STD_LOGIC)
b <=c; --legal (same “base” type: STD_LOGIC)
 ARRAY
Arrays are collections of objects of the same type.They can be one
Dimensional (1D),two dimensional (2D) or 1Dx1D.They can also be of
higher dimensions,but generally they are not synthesize.
0 Scalar(single bit)

01000 1D (vector)

01000 1.No predefined 2D or

01010 1Dx1D 1Dx1D arrays
2.To be Defined by the
11001 User
3.First defined new TYPE
0 0 0 0 0 Than new SIGNAL,
0 0 0 0 0 2D VARIABLE,or
CONSTANT can be
0 0 0 0 0
declared
 SYNTAX OF 2D AND 1Dx1D
ARRAY
TYPE type_name IS ARRAY (specification) OF data_type;
SIGNAL signal_name:type_name [:= initial_value]
--initial value is optional (used for simulation only)
EXAMPLE 1 : 1Dx1D
•Build an array containing 4vectors of size 8 bits
•1Dx1D array
•Call each vector by row
•Complete array by matrix
•Left most bit of each vector to be MSB
•Top row to be row0
So we have
TYPE row IS ARRAY (7 DOWNTO 0) OF STD_LOGIC;--1D array
TYPE matrix IS ARRAY (0 TO 3) OF ROW;--1Dx1D array
SIGNAL x:matrix;--1Dx1D signal
EXAMPLE 2 : 1Dx1D
Another way of constructing the 1Dx1D array of above constraint is
TYPE matrix IS ARRAY (0 TO 3) OF STD_LOGIC_VECTOR(7
DOWNTO 0);
SIGNAL x:matrix;--1Dx1D signal
EXAMPLE : 2D ARRAY
Notice that its construction is not based on vectors but on scalars
TYPE matrix2D IS ARRAY (0 TO 3,7 DOWNTO 0 )OF STD_LOGIC;
--2D array
EXAMPLE : 2D ARRAY
SIGNAL x : matrix := “0001”;--1D array
SIGNAL x : matrix := (‘0’,’0’,’0’,’1’);--1D array
SIGNAL x : matrix := ((‘0’,’0’,’0’,’1’),(‘1’,’1’,’1’,’0’));--1Dx1D array
--or 2D array
EXAMPLE : LEGAL AND ILEGAL ASSIGNMENT
TYPE row IS ARRAY (7 DOWNTO 0) OF STD_LOGIC;
-- 1Darray
TYPE array1 IS ARRAY (0 TO 3) OF row;
-- 1Dx1D array
TYPE array2 IS ARRAY (0 TO 3) OF STD_LOGIC_VECTOR(7
DOWNTO 0);-- 1Dx1D array
TYPE array3 IS ARRAY (0 TO 3, 7 DOWNTO 0) OF STD_LOGIC;
SIGNAL x : row;
SIGNAL y: array1;
SIGNAL v : array2;
SIGNAL w : array3;
-------------Legal scalar assignments :---------------------------
--the scalar (single bit) assignments below are all legal;
--because the “base” (scalar) type is STD_LOGIC for all signals
--(x,y,v,w).
x(0) <= y(1)(2);--notice two pair of parenthesis,y is 1Dx1D
x(1) <= v(2)(3); --two pair of parenthesis,v is 1Dx1D
x(2) <= w(2,1); --a pair of parenthesis,w is 2D
y(1)(1) <= x(6);
y(2)(0) <= v(0)(0);
y(0)(0) <= w(3,3);
w(1,1) <= x(7);
w(3,0) <= v(0)(3);
-------------------------------Vector assignments---------------------------------
x <= y(0);--legal (same data types:ROW)
x <= v(1);--illegal (type mismatch:ROW x STD_LOGIC_VECTOR)
x <= w(2);--illegal (w must Have 2D index)
x <= w(2,2 DOWNTO 0); --illegal (type mismatch:ROW x STD_LOGIC)
v(0) <= w(2); --illegal (w must Have 2D index)
y(1) <= v(3);--illegal (type mismatch:ROW x STD_LOGIC_VECTOR)
y(1)(7 DOWNTO 3) <= x(4 DOWNTO 0);legal (same type same size)
v(1)(7 DOWNTO 3) <= v(2)(4 DOWNTO 0);legal (same type same size)
w(1,5 DOWNTO i) <= v(2)(4 DOWNTO 0);illegal (type mismatch)
 PORT ARRAY
NO PRE –DEFINED DATA TYPES FOR MORE THAN 1D
BUT WE MIGHT NEED TO SPECIFY THE PORTS AS ARRAYS OF
VECTORS,SINCE TYPE IS NOT ALLOWED IN ENTITY
SOLUTION IS TO DECLARE USER-DEFINED DATA TYPES IN A
PACKAGE,WHICH WILL BE VISIBLE TO WHOLE DESIGN,
INCLUDING ENTITY.
-----------------------Package----------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.all;
--------------------------------------------------------------------------
PACKAGE my_data_types IS
TYPE vector_array IS ARRAY (NATURAL RANGE <>) OF
STD_LOGIC_VECTOR (7 DOWNTO 0);
END my_data_types;
----------------------------------------------------------------------------
---------------------Main Code---------------------------------------------
---------------------Main Code---------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE work.my_data_types.all;--user defined package
---------------------------------------------------------------
ENTITY mux IS
PORT (inp:IN VECTOR_ARRAY (0 DOWNTO 3);
. . .);
END mux;
...;
---------------------------------------------------------
•User-defined data type,called vector_array was created
•NATURAL RANGE <> means not fixed
•It is from 0 to 2,147,483,647
•Data types saved in PACKAGE called my_data_types
•Used in ENTITY to specify PORT called inp
•Additional USE clause to make the user-defined package my_data_type
Visible to the design
--------------------------Another option of PACKAGE-------------------
LIBRARY ieee;
USE ieee.std_logic_1164.all;
------------------------------------------
PACKAGE my_data_types IS
CONSTANT b: INTEGER :=7;
TYPE vector_array IS ARRAY (NATURAL RANGE <>) OF
STD_LOGIC_VECTOR (b DOWNTO 0);
END my_data_types

RECORDS
Records are similar to arrays,with only difference that they contain
objects of different types.
EXAMPLE:
TYPE birthday IS RECORD
Day:INTEGER RANGE 1 TO 31;
Month:month_name;
 SIGNED AND UNSIGNED DATA TYPES
These types are defined in std_logic_arith package
EXAMPLES:
SIGNAL x: SIGNED (7 DOWNTO 0);
SIGNAL y: UNSIGNED (0 TO 3);
--UNSIGNED value is a number never lower to zero
--Intended mainly for arithmatic operations
--Logical operations are not allowed
EXAMPLE:Legal and illegal operations
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;--extra package necessary
...
SIGNAL a: IN SIGNED (7 DOWNTO 0)
SIGNAL b: IN SIGNED (7 DOWNTO 0)
SIGNAL x: OUT SIGNED (7 DOWNTO 0)
...
V <= a+b; --illegal arithmetic operations not OK
w <= a and b;--legal (logical operations OK)
IEEE library provides two packages std_logic_signed
and std_logic_unsigned which allow operations with
STD_LOGIC_VECTOR data.
Example:
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;--extra package included
SIGNAL a: IN STD_LOGIC_vecTO (7 DOWNTO 0)
SIGNAL b: IN STD_LOGIC_vecTO (7 DOWNTO 0)
SIGNAL x: IN STD_LOGIC_vecTO (7 DOWNTO 0)
...
V <= a+b;--legal arithmetic operation OK),unsigned
W <= a and b;--legal logical operation OK
 DATA CONVERSION
Direct operations(arith,logi) between data of different types are not
Allowed.
SO conersion is required.
Done in two ways either user defined programme or invoking
FUNCTION from predefined functions.
If operand base is same but belong to different type classs than
std_logic_1164 library provides direct conversion.

TYPE long IS INTEGER RANGE –100 TO 100;

TYPE short IS INTEGER RANGE –10 TO 10;
SIGNAL x: short;
SIGNAL y: long;
...
Y<=2*x+5;--error,type mismatch
Y <=long(2*x+5);--OK,result converted into type long
--Several data conversion fuction can be find out in std_logic_1164
S.NO. FUNCTION FROM TO
1. Conv_integer(p) INTEGER INTEGER
UNSIGNED
SIGNED
STD_ULOGIC
2. Conv_unsigned(p,b) INTEGER UNSIGNED
UNSIGNED
SIGNED
STD_ULOGIC
3. Conv_signed(p,b) INTEGER SIGNED
UNSIGNED
SIGNED
STD_ULOGIC
4. Conv_std_logic_vecto INTEGER STD_LOGIC_
r(p,b) UNSIGNED VECTOR
SIGNED
STD_LOGIC
------EXAMPLE DATA CONVERSION-----
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
...
SIGNAL a: IN UNSIGNED (7 DOWNTO 0);
SIGNAL b: IN UNSIGNED (7 DOWNTO 0);
SIGNAL y: OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
...
Y<=CONV_STD_LOGIC_VECTOR ((a+b),8);
--Legal operations: a+b is converted from UNSIGNED to an 8-Bit
--STD_LOGIC_VECTOR value,then assigned to y

ASSIGNMENTS NOTE DOWN

4.OPERATORS
AND
ATTRIBUTES
 OPERATORS

•ASSIGNMENT OPERATORS
•LOGICAL OPERATORS
•ARITHMETIC OPERATORS
•RELATIONAL OPERATORS
•SHIFT OPERATORS
•CONCATENATION OPERATORS
Described in coming slides
<= USED TO ASSIGN A VALUE TO A SIGNAL
:= USED TO ASSIGN A VALUE TO A VARIABLE,CONSTANT OR
GENERIC.These all are used for establishing initial value
=>USED TO ASSIGN VALUES TO INDIVIDUAL VECTOR
ELEMENTS OR WITH OTHERS
EXAMPLE
SIGNAL x: STD_LOGIC;
VARIABLE y : STD_LOGIC_VECTOR(3 DOWNTO 0);
SIGNAL w: STD_LOGIC_VECTOR(0 TO 7);
Then the following assignment are legal:
x < = ‘1’;
y : = “0000”;
w <= “10000000”;
w <= (0 => ‘1’,others =>’0’);--LSB is 1 others are 0
 LOGICAL OPERATORS
Used for logical operations.Data must be of
TYPE BIT,STD_LOGIC, STD_ULOGIC and their respective
extensions that are BIT_VECTOR,STD_LOGIC_VECTOR,
STD_ULOGIC_VECTOR.The logical operations are
• NOT
• AND
• OR
• NAND
• NOR
• XOR
• XNOR –INTRODUCED IN VHDL93
EXAMPLE
y <= NOT a AND b;
y <= NOT (a AND b);
 ARITHMATIC OPERATORS
Used for arithmetic operations.Data must be of TYPE
INTEGER,SIGNED, UNSIGNED or REAL. If std_logic_unsigned and
std_logic_signed packages are included then STD_LOGIC_VECTOR
Can be employed directly in addition and subtraction (to be described)
+ Addition
- Subtraction
* Multiplication
/ Division
** Exponentiation
MOD modulus
REM Remainder Not Synthesiable
ABS Absolute value
 ARITHMATIC OPERATORS
Used for arithmetic operations.Data must be of TYPE
INTEGER,SIGNED, UNSIGNED or REAL. If std_logic_unsigned and
std_logic_signed packages are included then STD_LOGIC_VECTOR
Can be employed directly in addition and subtraction (to be described)
+ Addition
- Subtraction
* Multiplication
/ Division
** Exponentiation
MOD modulus
REM Remainder Not Synthesiable
ABS Absolute value
 COMPARISON OPERATORS
Used for making comparisons.Data must be of any TYPE listed above
The relational(comparison) operators are:
= equal to
/= not equal to
< Less than
> Greater than
<= less than or equal to
>= greater than or equal to
 SHIFT OPERATORS
Used for shifting data.Data must be of any TYPE listed above
SYNTAX
<left operand> <shift operation> <right operand>
Left operand must be BIT_VECTOR
Right operand must be INTEGER
SHIFT MEANING DEFINITIONS
OPERATORS
Sll Shift left logic Position on the right are filled with
0
Srl Shift right logic Position on the left are filled with 0
Sla Shift left Rightmost bit is replicated on the
arithmetic right
Sra Shift right Leftmost bit is replicated on the left
arithmetic
Rol Rotate left logic Rotate left logic
ror Rotate right logic Rotate left logic
 EXAMPLE
Say that x <=“01001”.Then
Y <= x sll 2; --y<=“00100”
Y <= x sla 2; --y<=“00111”
Y <= x srl 3; --y<=“00001”
Y <= x sra 3; --y<=“00001”
Y <= x rol 2; --y<=“00101”
 CONCATENATION
Are used to group values.The concatenation
operators are & and ,
Examples:
Z <= x & “1000000”;--if x=1 then z=11000000
Z=(‘1’,’1’,’0’,’0’,’0’,’0’,’0’,’0’); --z=11000000
ATTRIBUTES
• Allows VHDL more flexibility
• Allows GENERIC piece of code construct
ATTRIBUTES

Data Attributes Signal Attributes

 Data Attributes
Returns information regarding a data vector

S.No Data Attributes Information

.
D’LOW Return lower array index
D’HIGH Return upper array index
D’LEFT Return leftmost array index
D’RIGHT Return rightmost array index
D’LENGTH Return vector size
D’RANGE Return vector range
D’REVERSE_RANGE Return vector range in reverse
order
 Example-1
Consider the following signal:
SIGNAL D: STD_LOGIC_VECTOR (7 DOWNTO 0);
D’LOW=0,D’HIGH=7,D’LEFT=7,D’RIGHT=0,D’LENGTH=8,
D’RANGE=(7 DOWNTO 0),D’REVERSE_RANGE=(0 DOWNTO 7)
Example-2
Consider the following signal:
SIGNAL D: STD_LOGIC_VECTOR (7 DOWNTO 0);
Then all four LOOP statements below are synthesizable and equivalent
FOR I in RANGE (0 TO 7) LOOP . . .
FOR I in X’RANGE (0 TO 7) LOOP . . .
FOR I in RANGE (X’LOW TO X’HIGH) LOOP . . .
FOR I in RANGE (0 TO X’LENGTH-1) LOOP . . .
If signal is of enumerated type then:
D’VAL(pos):Returns position specified
D’POS(val): Returns position of the value specified
D’LEFTOF(val):Returns value in the position to the left of the value
specified
D’VAL(row,column):Returns value in the position specified
 SIGNAL ATTRIBUTES
Let us consider a signal s.Then
S.No. Attributes Information
S’EVENT Returns true when an event occars on s
S’STABLE Returns true if no event occars on s
S’ACTIVE Returns true if s=‘1’
S’QUIET<time> Returns true if no event has occurred
during the time specified
S’LAST_EVENT Returns the time elapsed since last event
S’LAST_ACTIVE Returns the time elapsed since last s=‘1’
S’LAST_VALUE Returns