Resolved Signals and

Generate Statement
Dr. Yann-Hang Lee
[email protected]
IEEE.std_logic_1164

type std_ulogic is (‘U’, ‘X’, ‘0’, ‘1’, ‘Z’, ‘W’, ‘L’, ‘H’, ‘-’);
subtype std_logic is resolved std_ulogic;

 std_logic is a resolved subtype of std_ulogic

 “resolved” is a resolution function
 if we declare
signal s1, s2: std_ulogic;
signal t1: std_logic;

s1 <= s2; -- s2 is the driver of s1

-- each signal can have one driver

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Resolved signals in VHDL

 Multiple outputs to drive one signal

 wired-or bus, tri-state connections
 if we write
t1 <= s1;
t1 <= s2;
 when t1 is assigned during a transaction, a resolution
function (i.e. “resolved”) is called to determine the
correct value based on all sources (i.e. s1 and s2)

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Resolved signals – std_logic

 type std_ulogic_vector is array (natural range <>) of std_ulogic;

 function resolved ( s : std_ulogic_vector ) return std_ulogic is

variable result : std_ulogic := 'z'; -- weakest state default
begin
if (s'length = 1) then return s(s'low);
else
for i in s'range loop
result := resolution_table(result, s(i));
end loop;
end if;
return result;
end resolved;

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Resolved signals – std_logic

type tri is (‘0’, ‘1’, ‘Z’);

type tri_ array is array (natural range <>) of tri ;
function resolved_func (t: in tri _vector) return tri is
variable result : tri := ‘Z’;
begin
for i in t’range loop
if t(i) /= ‘Z’ then
result := t(i);
end if
end loop
return result;
end function resolved_func;
signal s1: resolved_func tri;

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Composite Resolved Subtype

 in std_logic_1164:
type std_ulogic_vector is array (……) of std_ulogic;
 How about

type std_logic_vector1 is array (……) of std_logic;

subtype std_logic_vector2 is res_vector

std_ulogic_vector;
 one is an array of resolved subtype
the other is a resolved array

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Composite Resolved Subtype

 std_logic_vector1 is not a subtype of std_ulogic_vector

 std_logic_vector2
signal a: std_logic_vector2 (0 to 31);
signal b,c : std_ulogic_vector (0 to 31);
signal d : std_ulogic_vector (0 to 7);

a <= b;
a <= c;
a(0 to 7) <= d;

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 Resolved Signals and Ports

 Multiple out signals of unresolved type can be connected (in port

map) to a signal in signal of resolved type.
entity cpu is
port ( address : out uword; data : inout uword; -- . . . );
end entity cpu;

architecture top_level of computer_system is

signal address : uword;
signal data : word;
begin
the_cpu : entity work.cpu(behavioral)
port map ( address, data, -- . . . );
the_memory : entity work.memory(behavioral)
port map ( address, data, -- . . . );

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Resolved Ports

entity bus_module is
bus_based_system
port ( synch : inout std_ulogic; -- . . . ); synch_control
end entity bus_module;

architecture top_level of bus_based_system is bus-module_1 bus-module_2

signal synch_control : std_logic;

begin
synch_control_pull_up : synch_control <= 'H';
bus_module_1 : entity work.bus_module(behavioral)
port map ( synch => synch_control, -- . . . );
bus_module_2 : entity work.bus_module(behavioral)
port map ( synch => synch_control, -- . . . );
end architecture top_level;

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Resolved Ports
architecture behavioral of bus_module is
begin
behavior : process is
constant Tdelay_synch : delay_length := 10 ns;
constant wait_delay : delay_length := 100 ns;
begin
synch <= '0' after Tdelay_synch;
-- . . . bus_based_system
wait for wait_delay; synch_control
synch <= 'Z' after Tdelay_synch;
wait until synch = 'H';
-- . . . -- proceed with operation bus-module_1 bus-module_2

end process behavior;

end architecture behavioral;

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Object and its Driver

 Each signal object contains a value

 has one or more drivers
 If synch_control is inout, which value can you read
in
 after resolution
 before resolution – driving value
bus_module_1
resolution
driver1
function
bus_module_2
synch_control driver2

driver3

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Generate: example

ARCHITECTURE test_generate OF est_entity IS

SIGNAL S1, S2, S3: BIT_VECTOR(7 DOWNTO 0);
BEGIN
G1 : FOR N IN 7 DOWNTO 0 GENERATE
and_array : and_gate
GENERIC MAP (2 ns, 3 ns)
PORT MAP (S1(N), S2(N), S3(N));
END GENERATE G1;
END test_generate;

S2(7:0)
S1(7:0)

S3(7:0)

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Generate

 VHDL provides the GENERATE statement to create well-

patterned structures easily
 Some structures in digital hardware are repetitive in nature (e.g.
RAMs, adders)

 Any VHDL concurrent statement may be included in a

GENERATE statement, including another GENERATE
statement
 Specifically, component instantiations may be made within
GENERATE bodies
 Examples of usage:
 the instantiation and connection of half adders to make up a full
adder,
 exclusive or gates to create a parity tree.

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Generate: For scheme

 All objects created are similar

 The GENERATE parameter must be discrete and is

undefined outside the GENERATE statement
 Loop cannot be terminated early

name : FOR parameter_specification GENERATE

[Declaration_statements
BEGIN]
{concurrent_statements}
END GENERATE [name];

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A DRAM example
architecture chip_level of memory_board is
begin
bank_array : for bank_index in 0 to 3 generate
begin
nibble_array : for nibble_index in 0 to 3 generate
constant data_lo : natural := nibble_index * 4;
constant data_hi : natural := nibble_index * 4 + 3;
begin
a_DRAM : component DRAM
port map ( a => buffered_address,
d => DRAM_data(data_lo to data_hi));
end generate nibble_array;
end generate bank_array;
end architecture chip_level;

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A DRAM example (continued)

buffered_address

0-3 4-7 8-11 12-15

0-3 4-7 8-11 12-15

0-3 4-7 8-11 12-15

0-3 4-7 8-11 12-15

DRAM_data

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Generate If Scheme

 Allows for conditional creation of components

 Can generate conditional execution of timing checks.
 timing checks can be incorporated inside a GENERATE IF-
scheme.
Check_time : IF TimingChecksOn GENERATE
 Cannot use ELSE or ELSIF clauses with the IF scheme

name : IF boolean_expression GENERATE

[Declaration_statements
BEGIN]
{concurrent_statements}
END GENERATE [name];

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Example: serial-to-parallel SR
entity master_slave_flipflop is
port ( phi1, phi2 : in std_logic; d : in std_logic; q : out std_logic );
end entity master_slave_flipflop;

reg_array : for index in p_data'range generate

begin
first_cell : if index = 0 generate
begin
cell : component master_slave_flipflop
port map ( phi1, phi2, d => serial_data_in, q => p_data(index) );
end generate first_cell;

other_cell : if index /= 0 generate

begin
cell : component master_slave_flipflop
port map ( phi1, phi2, d => p_data(index - 1), q => p_data(index) );
end generate other_cell;
end generate reg_array;
Example: Parity generator

type TapPointArray_i is array (4 downto 0) of integer;

constant Tap_i : TapPointArray_i := (19, 15, 12, 4, 0);
par_fdbk_q(0) <= '0';

fdbk_q : for X in 0 to Tap_q'high generate -- parity generator

par_fdbk_q(X+1) <= par_fdbk_q(X) xor srl_q(Tap_q(X));
end generate fdbk_q;

19 15 12 4 0

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Recursive Structure

 A tournament tree
56

25 34 56 17

25 12 34 9 42 56 2 17

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Example (continued)
-- subtype num_type is SIGNED(7 downto 0);
-- type num_array is array(natural range <>) of num_type;
entity compare_node is
port ( clk: in std_logic; a, b : in num_type; y : out num_type);
end entity compare_node;
architecture action of compare_node is
begin
compare: process (clk) is
begin
if clk'event and clk='1' then
if a > b then
y <= a;
else
y <= b;
end if;
end if;
end process;
end architecture action;
Example (continued)
entity game_tree is
generic ( height : natural );
port ( output : out num_type:=x"00";
input : in num_array (0 to 2**height - 1);
clk: in std_logic);
end entity game_tree;
--------------------------------------------------
architecture recursive of game_tree is
begin
degenerate_tree : if height = 0 generate
begin
single: process (clk)
begin
if clk'event and clk='1' then
output <= input(0);
end if;
end process;
end generate degenerate_tree;
Configuration and Generate

configuration down_to_chips of memory_board is

for chip_level
for bank_array
for nibble_array
for a_DRAM : DRAM
use entity DRAM_4M_by_4(chip_function);
end for;
end for;
end for;
end for;
end configuration down_to_chips;

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Example (continued)
compound_tree : if height > 0 generate
signal buffered_input_0,signal buffered_input_1 : num_type ;
begin
node_0 : entity work.compare_node(action)
port map (clk=> clk, a => buffered_input_0,
b=> buffered_input_1, y => output );

subtree_0 : entity work.game_tree(recursive)

generic map ( height => height - 1 )
port map ( output => buffered_input_0,
input => input(0 to 2**(height - 1) - 1), clk=> clk);

subtree_1 : entity work.game_tree(recursive)

generic map ( height => height - 1 )
port map ( output => buffered_input_1,
input => input(2**(height - 1) to 2**height - 1),clk => clk);
end generate compound_tree;
end architecture recursive;