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Introduction To Processes: Dr. Yann-Hang Lee GWC 224 Yhlee@asu - Edu

The document provides an introduction to modeling processes in VHDL. It describes how processes are used to model sequential and concurrent behaviors. Key points include: - Processes contain sequential statements and are used to model behaviors over time. They execute when signals in their sensitivity list change. - Process execution pauses at wait statements until the wait condition is satisfied, then resumes. This allows processes to synchronize and communicate signal assignments. - Sensitivity lists and wait statements control when processes execute. Processes without wait statements model combinational logic, while those with waits can model clocked sequential circuits or communication between processes.

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23 views

Introduction To Processes: Dr. Yann-Hang Lee GWC 224 Yhlee@asu - Edu

The document provides an introduction to modeling processes in VHDL. It describes how processes are used to model sequential and concurrent behaviors. Key points include: - Processes contain sequential statements and are used to model behaviors over time. They execute when signals in their sensitivity list change. - Process execution pauses at wait statements until the wait condition is satisfied, then resumes. This allows processes to synchronize and communicate signal assignments. - Sensitivity lists and wait statements control when processes execute. Processes without wait statements model combinational logic, while those with waits can model clocked sequential circuits or communication between processes.

Uploaded by

Chutiya
Copyright
© © All Rights Reserved
Available Formats
Download as PPT, PDF, TXT or read online on Scribd
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Introduction to Processes

Dr. Yann-Hang Lee


GWC 224
[email protected]
Procedural Modeling USE:
High level abstraction of behavior

entity traffic_light_controller
generic ( yellow_time : time;
min_hwygreen : time;
max_hwyred : time );
port (
farmroad_trip : in boolean;
farmroad_light : out color;
highway_light : out color );
end traffic_light_controller;

architecture specification of traffic_light_controller is begin


...

CSE 422 page 2


Procedural Modeling USE:
High level abstraction of behavior
architecture specification of traffic_light_controller is begin
cycle: process is
begin
highway_light <= green;
farmroad_light <= red;
wait for min_green;
wait until farmroad_trip;
highway_light <= yellow;
wait for yellow_time;
highway_light <= red;
farmroad_light <= green;
wait until not farmroad_trip for max_hwyred;
farmroad_light <= yellow;
wait for yellow_time;
end process;
end specification;

CSE 422 page 3


Procedural Modeling Use: Detailed
Modeling of Behavior

Example: Timed Behavior of Primitive Elements


AND_n: process (x) is -- x is an array of bit
variable Zvar : bit;

begin
Zvar := ‘1’;
for i in x'range loop -- for every i in the range of x
if x(i) = '0' then
Zvar := '0' ;
exit ;
end if;
end loop;
Z <= Zvar after Tprop ;
end process AND_n;

CSE 422 page 4


Process Statement

Is the “wrapper” around a sequential routine to compute


the behavior desired for the design at a specific moment
in time.

label: process [ (signal list) ] is


{ declarations }
begin
{ sequential statements }
-- (typically ended by a wait statement)
end process [ label ];

CSE 422 page 5


Process Execution Model

 Executes once (at TIME = 0) -- initialization, running till it


hits a WAIT statement.
 Time advances until the wait condition is satisfied, then
execution resumes.
 Executes in an endless loop,
 interrupted only by WAIT statements;
 bottom of the process contains an implicit "go to
the top.”
 TIME DOES NOT ADVANCE within a process; it
advances during a WAIT statement.

CSE 422 page 6


Process Statement
- A Concurrent Statement
 A process is a kind of concurrent statement.
 includes declarations, sequential body, and all

 Evaluation of a process is triggered when one of a list of


signals in the wait statement changes value
 Note: Just because a process is sequential does NOT
mean it is modelling the sequential behavior of a design.
 a description of functional behavior
 For example: the AND_n process example is the model of a
combinational logic element.

CSE 422 page 7


Lab 0 – an exercise

library IEEE;
use IEEE.std_logic_1164.all;

entity andcircuit is
port(
in1, in2, in3 : in std_ulogic;
out1 : out std_ulogic
);
end andcircuit;

CSE 422 page 8


Lab 0 – an exercise (continued)

architecture andc of andcircuit is


signal net1 : std_ulogic;

begin
process (in1, in2)
begin
if (in1 = '1' and in2 = '1') then
net1 <= '0' ;
elsif (in1 = '0' or in2 = '0') then
net1 <= '1' ;
end if;
end process;

CSE 422 page 9


Lab 0 – an exercise (continued)

process (net1, in3) wait for 15 ns;


begin in2 <= '1' ;
if (net1 = '1' and in3 = '1') wait for 15 ns;
then out1 <= '0' ; in3 <= '1' ;
else wait for 15 ns;
out1 <= '1' ; in1 <= '0' ;
end if; wait for 15 ns;
end process; in2 <= '0' ;
wait for 15 ns;
process in3 <= '0' ;
begin wait for 15 ns;
in1 <= '1' ; end process;
end andc;

CSE 422 page 10


Initialization of Objects

 Signals, variables, constants can all be set to default values:


signal enable : bit := 0;
variable Fval : std_logic := '0';
constant Tplh : Time := Tprop + K * load ;
where Tprop, K, load are generics or constants,
 Ports can be initialized by
entity xyz port ( a : in bit := '0'; . . . )

Even so, this is not enough to fulfill all the requirements for
initializing a model.

CSE 422 page 11


Signal assignment

 Signals
 Used to communicate between concurrently
executing processes.
 Within a process they continue to have the form
sig <= waveform ;
 Means that for the signal a sequence of value
updating events is to be scheduled for the future.

CSE 422 page 12


Variable assignment

 Variables:
 Exist within procedural bodies, like processes,
functions, and procedures. Not visible to others.
 Variable assignment statements appear as follows:
var := expression;
 Used within the sequential body just as in other
procedural languages.

X <= Y; X := Y;
Y <= X; Y := X;

CSE 422 page 13


Misuse of Sequential Signal
Assignments
 Note that a signal does not take on its new value
until time advances.
 Until the process hits a WAIT (hold, or suspend)
statement, simulation time does not advance,
 Therefore, the signal will never be updated before
the WAIT
 and may not be updated even after the WAIT is
complete if the WAIT completed faster than the signal
update has delay associated with it.

CSE 422 page 14


Wait Statements

Two primary forms of WAIT condition.


 wait on signal_list ;
 The signal_list is also called the sensitivity list . The
process will resume execution whenever an event
occurs on one of those signals.
 wait until condition ;
 The condition will be evaluated whenever one of the
signals in that boolean expression changes value,
but execution of the process does not resume until
the condition evaluates TRUE.

CSE 422 page 15


Wait Statements

 wait for time_expression ;


where time_expression represents the time interval before
execution of the process resumes. Note that time_expression
is not absolute time, but time relative to the time at which the
current execution of the process took place.

CSE 422 page 16


Use of Multiple Wait Statements

 Signal assignments combined with WAIT statements


give the ability to create communicating sequential
processes.
 However,
 synthesis tools do not usually allow the use of
multiple WAIT statements within a process, and
 processes are usually restricted to modeling either
combinational logic or clocked sequential circuits.

CSE 422 page 17


Example Use of Multiple Wait Statements:
CPU and Memory Handshaking

Memory: process is
begin
DAV <= '0';
wait until Mem_Req = '1';
Data <= ROM_DATA(Address) after 50 ns;
DAV <= '1' after 60 ns;
wait until Mem_Req = '0';
end process;
CPU_Read: process is
begin
Mem_Req <= '0';
wait until ... the need for memory read ;
Address <= . . . address value . . .
Mem_Req <= '1' after 10 ns;
wait until DAV = '1';
MD_Reg <= Data;
end process;
CSE 422 page 18
label: process ( a, b, c, d ) is
where signals a, b, c, d are the sensitivity list

 is equivalent to a single WAIT with a sensitivity list at


the bottom of the process:
process
begin
.......
wait on a, b, c, d;
end process;
 Whenever any of the signals in the sensitivity list
change value, the process will be executed.
 Note: Processes with a sensitivity list may not
contain any wait statements, nor may they call
procedures with wait statements.

CSE 422 page 19

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