Cadence Tutorial

-- Presented by
Chaitanya Emmela
cxe1177@cacs
VLSI Research Group
CACS
Contents
 Setting up the Cadence
 Usage
 Schematic  Layout
 Layout  Extracted View
 Extracted View  Simulation
 Conclusion
 Future Work
 Acknowledgements
 Questions
Setting up the Cadence

 Create a working Directory, where all your projects

will be stored.
 Copy all the files, including the dot files from the
“imp_files” directory.
 Create alias, say stmhsll for stmhsll.cshrc in the
.cshrc file.
 Source the .cshrc file. The stmhsll (stmllull) file sets
environment and path for the Cadence STM for high
speed and low leakage (low leakage and ultra low
leakage) designs.
Usage

 Type in the command: cd working_dir (Figure

1).
 Type in the command: stmhsll (alias set up
for stmhsll.cshrc, in the .cshrc file).
 Type in the command to start cadence tool:
icfb& (Figure 1).
Usage

Figure 1: Terminal Window

Usage

Figure 2: ICFB
Usage

Figure 3: Library Manager

Usage

 Go to “Tools  Library Manager”, which

starts the Library Manager (Figure 3).
 This window should show CORE9GPHS,
CORE9GPLL, CORX9GPHS,
CORX9GPLL, DK_process_013u,
IOLIB_65_3V3_m6_LL_65A,
IOLIB_65_M6_LL, PR9M6, REG9GPHS,
REG9GPLL, STlib, analogLib,
device_symbols and device_symbols_a.
Usage

Figure 4: New Library

Usage

Figure 5: Attaching Tech File to New Lib

Usage

 To create a new library “File  New 

Library”, this pops a new window as shown
in the Figure 4.
 Attach to existing Tech Library to the New
Library created as shown in the Figure 5
(DK_process013u). Click Ok.
Usage

Figure 6: Create New Cell View

Usage

 Create a New cell view; “File  New  Cell

View”, this will open a window which is
shown in Figure 6. Clicking Ok opens up a
schematic editor (for drawing the Schematic
of the circuit being designed as shown in the
Figure 7).
Schematic  Layout

Figure 7: Schematic
Schematic  Layout

 During the Schematic remember to define the

Vdd and Gnd as Bidirectional pins. Once you
are done with the Schematic do check and
save.
Schematic  Layout

Figure 8: Layout XL
Schematic  Layout

 Then use the Layout XL for the layout from

“Tools  Design Synthesis  Layout XL”.
Create New or open existing one (Figure 8).
Click Ok and it opens up a new Window,
“Layout XL”.
Schematic  Layout

Figure 9: Generate from Source

Schematic  Layout

 Click “Design  Generate from Source”, to get a

window (Figure 9) to generate the pmos, nmos and
the pins in the schematic to Layout.
 Choose “Metal1” as the Layer and click on Apply.
 Generally, the width of Gnd and Vdd used is 0.78.
Do not forget to click on Update or the changes will
not be applied.
 The Boundary height is fixed at 6.5 and the design
can stretch horizontally.
 Click Ok. The output of the Gen. from Source is
given in Figure 10.
Schematic  Layout

Figure 10: Output of Gen. from Source

Schematic  Layout

Figure 11: Component Types

Schematic  Layout

 Click “Design  Component Types”, this

opens a window for creating component
types (Figure 11). Use Capitals for the
Component type names.
 Type in the Component name in the “Type”
text box and click Add. For e.g. Type:
PHSMOS/NHSMOS.
 Choose the Component Class PMOS/NMOS,
as appropriate.
Schematic  Layout

Figure 12: Fold Threshold

Schematic  Layout

Figure 13: Source Terminal

Schematic  Layout

Figure 14: Drain Terminal

Schematic  Layout

Figure 15: Gate Terminal

Schematic  Layout

Figure 16: Bulk Terminal

Schematic  Layout

Figure 17: Active layer

Schematic  Layout
 In the Edit parameters section, use the following for the various
options: - Width Par Name : w, Fold Threshold : 5, Source
Terminal : S, Drain Terminal : D, Gate Terminal : G, Bulk Terminal
: should be B but leave blank as the Standard PMOS and NMOS
cell we are using has no Bulk, we have to create one, Active
layer : active drawing (Active dg). This is shown in the Figures
11, 12, 13, 14, 15, 16 and 17.
 Select “device_symbols phsmos”/”design_symbols nhsmos” from
the “Cells in selected scope” section on the left and using “>>>”
button add it to “Components in Type” section on the right.
 Click Ok after all the above options have been set.
Schematic  Layout

Figure 18: Pin Placement

Schematic  Layout

 Click “Place  Pin Placement” and it opens

up a dialog box shown in Figure 18. Do the
Following for placing the pins in the layout.
 Click on the “Link to Layout” Button which
turns into “Unlink from Layout” Button as
shown in the Figure 18.
 Click on the “Schematic View” in the “Place
pins as in” section.
Schematic  Layout

Figure 19: Output from Pin Placement

Schematic  Layout

 Select gnd! and vdd! separately from the Pin

Name section and click on the “HRail” Button
which turns into “unHRail”. Click Ok. The
output from the Pin Placement is shown in
Figure 19.
Schematic  Layout

Figure 20: PPART Partitioning

Schematic  Layout
 Click “Place  Partitioning”, which pops up a window shown in
Figure 20. This is used to create partitions.
 In the section “Choose or type a Partition name”, type the name of the
partition one would like to create for e.g. PPART/NPART and click on
“Create Partition”.
 Click on the “Link to design” which turns into “Unlink”.
 Choose “Softfence (SoftFnc dg) from the LSW window (Figure 21).
 Create a rectangle (“Create  Rectangle”) inside the Boundary area
of the Design (between Vdd and Gnd).
 Click on “Attach Shape” and click on the rectangle drawn on the layout
window.
 If the shape is attached the “Detach Shape” will be activated. (Incase
this doesn't happen just check whether the “Link to Design” button is
showing "Unlink", otherwise click on "Link to Design".)
Schematic  Layout

Figure 21 -- LSW
Schematic  Layout

Figure 22: NPART Partitioning

Schematic  Layout

 Select the MOSFETS in the Component

names and move the components by clicking
the Move button and choosing the right
Partition from the “Target Partitions” section
(PMOS in PPART and NMOS in NPART).
The NPART Partitioning is shown in Figure
22.
 After shifting all the MOSFETS to respective
partitions, Click Ok.
Schematic  Layout

Figure 23: Placement Planning

Schematic  Layout

 Click “Place  Placement Planning”, and a

window shown in Figure 23 opens up.
 Incase the Partitions are created choose the
required partition or else the default is
Boundary.
 Choose the “Components” tab and change
the Option for “Align Components” to
"Outside".
 Click on Calculate Estimates Button on the
lower left corner.
Schematic  Layout

Figure 24: Output of Placement Planning

Schematic  Layout

 This will calculate the number of NMOS and

PMOS in the design and the area in which it
will be placed inside the boundary area
(Figure 24). Click Ok.
Schematic  Layout

Figure 25: Placer

Schematic  Layout

 Click on “Place  Placer”, to open the

window shown in Figure 25.
 Select the Options (apart from the already
activated ones), “Group CMOS Pairs” and
“Optimize Placement”.
 Click on the “Set File” button (for the rules
file) and select Placer.rul from the Browse
window. Click Ok.
Schematic  Layout

Figure 26: Output from Placer

Schematic  Layout

 Incase the Placer gives an error just close

the placer and restart it. This should work.
 After placing is done, just verify that all the
I/O pins are outside the PMOS and NMOS
region, if not then manually shift them out
(Figure 26).
Schematic  Layout

Figure 27: Export to Router

Schematic  Layout

 Click “Route  Export to Router”, which

opens a window “Export to Router” (Figure
27).
 In the “Routers” section, select "Cadence
chip assembly router", the other option will
give license error. Click Ok.
Schematic  Layout

Figure 28: Router

Schematic  Layout

 Incase this gives an error, close ICFB and

restart it, and try the “Router  Export to
Router”, this should work (just check that the
option "Cadence chip assembly router" is
selected in the “Routers” section. A new
window opens up (Figure 28).
Schematic  Layout

Figure 29: Router

Schematic  Layout

 Goto “Autoroute  Detail Router  Detail

Route”, this opens a window (Figure 29)
where one can specify the number of passes.
Click Ok. This will route the whole design.
The output is shown in Figure 30.
Schematic  Layout

Figure 30: Output from Router

Schematic  Layout

Figure 31: Clean

Schematic  Layout

 In case one doesn't like the Routing, one can

use “Autoroute  Clean”: where one can
specify the number of passes, if one wants to
(Figure 31). Click Ok. This will clean the
Routing, like try to remove higher layers of
metal, if possible, etc (Figure 32).
Schematic  Layout

Figure 32: Output from Clean

Schematic  Layout

Figure 33: Routing Done

Schematic  Layout

 When the routing seems fine save it and

exit. This will save the Routing in the
Layout Window (Figure 33).
Schematic  Layout

Figure 34: Adding PTAP and NTAP

Schematic  Layout

 Add Instance of NTAP and PTAP, “Create

 Instance” (the number depends on the
size of the design).
 For arraying a row of NTAP/PTAP, just fill in
the number in the Columns section and the
Delta X section for the space between each
NTAP/PTAP (Figure 34). Click Hide.
Schematic  Layout

Figure 35: Creating Nwell

Schematic  Layout

 Choose Nwell (Nwell dg) from the LSW

window and using “Create  Rectangle”,
Create nwell as shown in Figure 35.
Layout  Extracted View

Figure 36: Extractor

Layout  Extracted View

 Click “Verify  Extract”, to view the window

as shown in Figure 36.
 Specify the “Extracted” name, in the “View
Names” Section, if not mentioned default is
"extracted".
 Specify the Rules file as "divaDRCEXT.rul", in
the “Rules File” Section.
 Set switches as extPAR_CapSingleNode, in
the “Switch Names”, by pressing “Set
Switches” button. Click Ok.
Layout  Extracted View

Figure 37: Extracted View

Layout  Extracted View

 This gives an extracted view of the design (Figure

37).
 Incase the extracted view has some error as "pin
in layout not in extracted view", then this is
problem and one may have to do the whole
procedure again, maybe including changes in
Schematic.
 Close the Layout (without saving), as one has the
extracted view already. This will also help in
generating many extracted view using the same
layout.
Extracted View  Simulation

Figure 38: Spectre

Extracted View  Simulation

 From the “Library Manager”, open the

“Extracted View” (Usually stored above the
layout and schematic for the “cell view”).
Click “Tools  Analog Environment”,
opens up Cadence Analog Design
Environment (Figure 38).
Extracted View  Simulation

Figure 39: Simulator Directory

Extracted View  Simulation

 Click “Setup 
Simulator/Directory/Host”, to setup the
simulator directory. Choose “spectre”
option in the “Simulator” section (Figure 39).
Choose the “Project Directory” as
“./simulation” (usually default is
~/simulation, don’t forget to change this to
./simulation, this will create simulation files
local to the project). Click Ok.
Extracted View  Simulation

Figure 40: Model Libraries

Extracted View  Simulation

 Click “Setup  Model Libraries”, to setup

the Model Libraries for the Spectre
Simulation (Figure 40). Click on Browse
button to add one by one,
common_active.scs, common_go1.scs,
common_ploy.scs and mos.scs, in the same
order as given, from the Corners Directory,
(will be in the imp_dot_files directory copied
during the setup or from the original Setup
directory) all with the Section TT. Click Ok.
Extracted View  Simulation

Figure 41: Simulation Files

Extracted View  Simulation

 Click “Setup  Stimuli”, for providing

input values to the input signals. If this
doesn't work, then try “Setup 
Simulation Files” (Figure 41).
 Specify the Stimulus File (like for e.g.,
"./fa.scs"), in the Stimulus File section.
Extracted View  Simulation

 Note the format for the pulse from the following

example:

 V0 (A 0) vsource dc=1.2 type=pulse val0=0.0 val1=1.2

period=1n delay=0 rise=100p fall=100p width=500p
 V1 (B 0) vsource dc=1.2 type=pulse val0=0.0 val1=1.2
period=1n delay=3n rise=100p fall=100p width=500p
 V2 (Cin 0) vsource dc=1.2 type=pulse val0=0.0 val1=1.2
period=2n delay=0 rise=100p fall=100p width=1n
 V3 (vdd! 0) vsource dc=1.2 type=dc
Extracted View  Simulation

Figure 42: Analyses

Extracted View  Simulation

 Click on “Analyses  Choose”, a window

opens up as shown in Figure 42. Choose
the radio option "tran" for “transient
analysis”, in the “Analysis” section.
 Choose the “Stop Time” say "10n".
 Choose the Accuracy Defaults as Moderate
and just be sure that the enabled is
activated. Click Ok.
Extracted View  Simulation

Figure 43: Save Options

Extracted View  Simulation

 Choose “Outputs  Save all”, and click

on all for “select power signals for output”
and “select device currents” sections
(Figure 43).
Extracted View  Simulation

Figure 44: Netlist

Extracted View  Simulation

 Click on “Simulation  Netlist and Run”.

This will open a window. Click Ok. If this
gives any error try copying the CORNERS
Directory into Your Project Directory.
 One can see the Netlist by clicking
“Simulation  Netlist  Display”. This
will open the netlist in a new window (Figure
44).
Extracted View  Simulation

Figure 45: Waveform Window

Extracted View  Simulation

 To view the waveform, go to “Results 

Direct plot  Transient Signal”.
 Just select the signals (pins, both input and
output) from the “Extracted View” window
and press "ESC" keeping the pointer in the
“Waveform Window”. This will plot the
waveform in the waveform window (Figure
45).
Extracted View  Simulation

Figure 46: Browse Project Hierarchy

Extracted View  Simulation

 More Analysis can be done using “Tools 

Results Browser”. A window opens as
shown in the Figure 46. Click Ok. This will
open another window as shown in Figure
47. In the “Result Browser” window, click
on the “Extracted_name  psf  tran-
tran”, Figure 48.
Extracted View  Simulation

Figure 47: Result Browser

Extracted View  Simulation

Figure 48: Tran-Tran

Extracted View  Simulation

Figure 49: Calculator

Extracted View  Simulation

Figure 50: Waveform Window Function

Extracted View  Simulation

 This gives Pwr, Currents (ID, IB, etc), etc.

Double click any of these, which open up in
calculator (Figure 49) by which one can do
lot of operations on them like average,
integrate, etc. Click on the required Special
Function using the “Special Function”
button and clicking plot to plot that function
on “Waveform Window” (Figure 50).
 Click on the “Extracted_name  psf 
finalTimeOP-info” (Figure 51).
Extracted View  Simulation

Figure 51: FinalTimeOP-Info

Extracted View  Simulation

Figure 52: Saving State

Extracted View  Simulation

 This gives the values for Vds, Vth, Ids, and

many more values regarding the various
MOSFETs used. Double click any of these
to see the Value.
 Before closing the Design environment,
save the state so that it helps the next time
one has to use the tool. Click “Session 
Saving State”, which opens a dialog box
as shown in Figure 52.
Conclusion

 Schematic to Layout Automated

 Extracted View from Layout, does a better
extraction and gives all parasitic
capacitances.
 Simulation from extracted view using
Spectre.
 Detailed analysis available apart from
Waveform, like power, Ids, etc.
 Documentation completed and submitted.
Future Work

 Compaction
 PLS Extract
 Abutment
Acknowledgements

 Dr. Bayoumi
 Soumik
 ST Microelectronics
Questions ????
Thank You !!!!