IAY0600

DIGITAL SYSTEMS DESIGN

Digital Systems Design Overwiev

IAY0600 Course Labs` Organization
XILINX ISE Design Suite Overwiev
Dmitri Mihhailov
Tallinn University of Technology
Digital Systems Design
 Implementation possibilities:
Application-specific integrated circuits (ASICs)
Programmable logic devices (CPLDs, FPGAs)
Processor
General purpose processors
Special purpose processors (DSP, GPU)
 Digital Systems Design is a trade-off:
Time-to-market
Cost
Silicon Area
Performance
Power consumption
Development Complexity 2
Application-specific integrated circuits
 ASIC is an integrated circuit that is
specifically designed for certain
application
 ASIC development flow:
Design
Verification
Fabrication
Packaging
Testing
Refabrication (errors, change in specification)
Software development
3
ASIC design technolgies

 Full Custom
 Gate Array

 Standard Cell

 Structured

4
Full Custom ASICs [1]

development from
scratch
complete control
over each layer
may include analog
circuitry
special tools
highly complex and
time consuming
allows highest
optimization
[1] https://en.wikipedia.org/wiki/Application-specific_integrated_circuit#Full-
custom_design 5
Gate array ASICs [2]
basic cells are
premanufactured
only connections
are needed
fabrication is done
much faster and
cheaper
standard tools and
component libraries
lower density and
performance
almost obsolete
[2] Clive Maxfiel, Bebop to the Boolean Boogie. An Unconventional Guide
to Electronics, 2nd Edition, Newnes, 2003 6
Standard cells ASICs [2]
standard cells are
predesigned
finding optimal
placement and
routing is needed
full fabrication cycle
standard tools and
component libraries
close to optimal
higher abstraction
IP cores
dominant technique
[2] Clive Maxfiel, Bebop to the Boolean Boogie. An Unconventional Guide
to Electronics, 2nd Edition, Newnes, 2003 7
Structured ASICs [3]
premanufactured
base tiles/modules
and RAMs, PLLs,
clock trees, etc.
only connections
are needed
fabrication is done
much faster and
cheaper
standard tools and
component libraries
lower performance
[3] Clive Maxfield. (2004) The Design Warrior's Guide to FPGAs, Academic
Press, Inc. Orlando, FL, USA 8
Programmable logic device technolgies

 Simple
Programmable Logic Devices
(SPLDs)
PROM
PLA
PAL
etc.
 Complex Programmable Logic
Devices (CPLDs)
 Field
Programmable Gate Arrays
(FPGAs)
9
Simple programmable logic device [3]
 Programmable logic array (PLA)

allows Sum of Products (SoP) implementation

[3] Clive Maxfield. (2004) The Design Warrior's Guide to FPGAs, Academic
Press, Inc. Orlando, FL, USA 10
Complex programmable logic device [4]

[4] CoolRunner-II CPLD Family Data Sheet, DS090 (v3.1). September 11,
2008 11
Field-programmable gate array (1)
 FPGA is an integrated circuit that
contains (re)configurable blocks of logic
and (re)configurable interconnect.
 Field-programmable means that
(re)configuration can be done “in field”
(even when device is already deployed)
 FPGA development flow:
Design
Verification (functional and hardware)
Redesign (errors, change in specification)
Software development 12
Conceptual structure of an FPGA [5]

[5] Chu, P. P. (2008) References, in FPGA Prototyping by VHDL Examples:

Xilinx Spartan™-3 Version, John Wiley & Sons, Inc., Hoboken, NJ, USA 13
Three-input LUT-based logic cell [5]

[5] Chu, P. P. (2008) References, in FPGA Prototyping by VHDL Examples:

Xilinx Spartan™-3 Version, John Wiley & Sons, Inc., Hoboken, NJ, USA 14
Three-input LookUp Table (LUT) (1) [3]

[3] Clive Maxfield. (2004) The Design Warrior's Guide to FPGAs, Academic
Press, Inc. Orlando, FL, USA 15
Three-input LookUp Table (LUT) (2)

16
Three-input LookUp Table (LUT) (3)

write out Sum of Products (SoP) and product of

Sums (PoS) representations
17
Field-programmable gate array (2)
 Other FPGA components:
Dedicated carry logic and interconnect
Embedded RAMs (dual-port)
DSP blocks (dedicated adder, multipliers, etc.)
Processor cores
Dedicated clock tree and clock managers
Configurable GPIOs (voltage, impedance)
Gigabit transceivers
SRAM-based configuration (also FLASH-based)
 The main FPGA manufacturers:
Xilinx and Altera ??? (acquired by Intel)
Lattice, Microsemi (Actel), SiliconBlue, Achronix,
QuickLogic, Tabula (approx. 20% of the market) 18
ASICs vs FPGAs
Time-to-market
Faster for FPGA (no fabrication required)
Cost
FPGA is cheaper for low-volume production
Silicon Area
ASICs need less for the same functionality
Performance
ASICs generally offer better performance
Power consumption
ASICs are more power efficient
Development Complexity
FPGAs are easier to design with

 FPGA can be used to prototype ASIC 19

FPGAs vs Processors
Cost, Silicon Area, Power consumption
Comparable
Time-to-market
Faster for Processors (only software is required)
Performance
FPGAs outperform only in case of massive parallelism
Development Complexity
Processors are easier to design with

 Onthe whole Processors tend to be

a better option (if applicable)

20
Designing Digital Systems
 Digital Design entry:
Schematic
HDLs (VHDL, Verilog, SystemVerilog)
High-level synthesis (C, C++, SystemC)
 Digital Design with HDLs:
Logic gate level
Register Transfer Level (RTL)
Use synthesizable SUBSET of HDL
 Designer should “help” the tool:
Consider the technology
Employ recommended coding style
Be as specific and clear as possible 21
Designing with FPGAs
 FPGAsare likely to benefit from logic
redundancy-based techniques:
pipelining, one-hot FSM state encoding,
resource duplication instead of sharing, etc.
 Logic gate-based optimization are
likely to be inefficient for FPGAs
LUTs are used to implement combinational logic
 Asynchronous design is generally
not suited for FPGAs
avoid use of latches, asynchronous structures,
combinational loops, etc. 22
 IAY0600

DIGITAL SYSTEMS DESIGN

IAY0600 DIGITAL SYSTEMS DESIGN LABS

Dmitri Mihhailov
Tallinn University of Technology
Digital Systems Design Labs Staff
 Lecturer:
Alexander Sudnitson (associate professor)
[email protected]
ICT-503 (620 2255)
 Lab Assistant:
Dmitri Mihhailov (research scientist)
[email protected]
ICT-505 (no phone)
 Technical Assistant:
Artjem Rjabov (early stage research scientist)
[email protected]
ICT-512 (620 2265) 24
IAY0600 Digital Systems Design Labs (1)
 Lab Room:
ICT-502AB (~ 30 working places)
ICT-405 (15 working places)
Lab PCs require the same password that is used
to access other computers in TUT network
 Lab Time:
GROUP A
Wednesdays 16:00 - 17:30 (primary time)
ICT-502AB
GROUP B
Wednesdays 17:45 - 19:15 (reserve time)
ICT-405
25
IAY0600 Digital Systems Design Labs (2)
 Lab Course webpage:
http://ati.ttu.ee/~alsu/
IAY0600l Digital Systems Design
(WORKSHOPS)
http://ati.ttu.ee/~alsu/IAY0600l.html
 The target lab course:
LABS SET I (Xilinx FPGA-based)

 The lab course consists of 10 labs:

Tutorial (essentially not a lab)
Set of compulsory labs (4 labs)
Set of optional labs (5 labs)
26
Overview of the Lab Types
 Tutorials:
Introduce the working flow of design tools
Optional
 Compulsory labs:
Form the basic core of the course
MUST be completed within deadline
Yield minimum positive final grade
Allow possibility to attend the exam
 Optional labs:
Form the advanced core of the course
NOT REQUIRED to pass the course
Increase the final grade 27
LABS SET I (Xilinx FPGA-based)
 Lab1 (Tutorials)
 Compulsory labs (+30 points):
Lab 2 (Comparator)
Lab 3 (Adder)
Lab 4 (Parameterizable Adder)
Lab 5 (Shift Register)
 Optional labs (+60 points in total):
Lab 6 (Finite State Machine) +20 pts.
Lab 7 (Greatest Common Divisor) +10 pts.
Lab 8 (Linear Feedback Shift Register) +10 pts.
Lab 9 (Creeping Line) +10 pts.
Lab 10 (RISC Processor) +10 pts.28
List of General Lab Requirements
 General lab requirements (NOT final):
The deadline is 16th week (all labs)
One extra DEFENSE ONLY session may be
added during the first week of examination
session
Labs are done either INDIVIDUALLY, or in
teams of TWO students
Labs are passed in the same order as they are
listed on the webpage
Lab manuals DO NOT feature all the necessary
information for solving the task
Some lab manuals feature TASK description
and EXAMPLE solution of a similar task 29
How to Pass a Lab
 Step 1 (Visual Demonstration):
Working prototype is examined for
functional correctness during lab session
 Step 2 (Report, INDIVIDUAL):
Submit the following to [email protected]
(cc: [email protected]):
Lab report (PDF)
Source files (*.vhd, *.sch, *.ucf)
Wait for acknowledgment of acceptance
 Step 3 (Defense, INDIVIDUAL):
Book a slot for defense during lab session
Be ready to answer ANY questions 30
How to Write a Report
 Reports are written in FREE form
 The goals of lab report:
Document the workflow
Describe the results and their significance
Demonstrate writer’s comprehension
 List of topics to cover in the report:
Introduction
Background
Workflow
Results and discussion
Conclusion (including feedback)
References and appendices 31
List of General Report Requirements
 General report requirements (NOT
final):
Lab report MUST feature things that are
specifically required to be included in the task
All objects in the text MUST be numbered,
labeled and referenced
All concepts, statements, results MUST be
explicitly described in verbal form within text
Complete source codes MUST NOT be part of
the report (even in appendices)
Functional simulation MUST always be
performed and described
32
Design Tools and Equipment in the Lab
 Xilinx Design Software:
ISE Design Suite (7-series and older)
 System Edition (in the lab)
 WebPACK Edition (free)
Vivado Design Suite (7-Series and newer)
 System Edition (in the lab)
 WebPACK Edition (free)

 FPGA boards:
Digilent Nexys-3 (Xilinx Spartan-6 FPGA)
 used for labs 2-5
Digilent ZedBoard (Xilinx Zynq-7020 FPGA)
 used for labs 5-10
 replaced with Digilent Nexys-4 (Xilinx Artix-7 FPGA) 33
 IAY0600

DIGITAL SYSTEMS DESIGN

XILINX ISE DESIGN SUITE OVERVIEW

Dmitri Mihhailov
Tallinn University of Technology
Xilinx ISE Design Suite
 Project Navigator is graphical interface
for project and design management
 Project Navigator GUI:
Sources window (top left)
Processes window (middle left)
Workspace window (top right)
Console Message window (bottom)
 Project Navigator tools:
PlanAhead
ISim
XPower Analyzer
iMPACT 35
Project Navigator GUI

36
Project Navigator Sources Window
1

2
1 Design views
Implementation
Simulation
2 Top-level module marker 37
Project Navigator Processes Window (1)

 Main design processes:

Design Summary
Design Utilities
User Constraints
38
UCF Pin Assignment in Text Editor

 Format of Pin Assignment in UCF:

NET “design_pin_name” LOC = FPGA_pin_number;
39
Project Navigator Processes Window (2)

 Synthesize process:
Performs logic synthesis (HDL constructs are
transformed to generic digital components)
View RTL and Technology Schematics
Check Syntax
Generate Post-Synthesis Simulation Model
40
Project Navigator Processes Window (3)

 Implement Design processes:

Translate - creates a single design netlist
Map - maps logic to FPGA components
PaR - derives physical layout within FPGA
Generate Post-... Simulation Model
Timing and Power Analysis
41
Xilinx XPower Analyzer

 XPower Analyzer tool overview:

Report thermal information
Report static and dynamic power consumption
Identify areas where power can be reduced
42
Project Navigator Processes Window (4)

 Generate Programming file process:

Set FPGA start-up clock to JTAG Clock
 Configure target device process:
iMPACT tool
 Analyze Design process:
ChipScope tool
43
Xilinx iMPACT Configuration Tool

 Configure FPGA device:

Select Boundary Scan iMPACT flow
Initialize JTAG chain
Set appropriate *.bit file to FPGA (skip SPI/BPI)
Program FPGA device 44
Project Navigator Processes Window (5)

 Simulation view:
Simulate design at different steps in design flow

 Simulation process:
ISim tool
45
Xilinx ISim Simulator Tool

1 2
1 ISim Simulator windows:
Simulation Objects (no variables)
Instances and Processes
Waveform
2 Re-launch button 46
Project Navigator Workspace Window
1

1 Language Templates
2 Float Window
47
Project Navigator Console Window

 Console views:
Console (shows all messages)
Errors (shows only error messages)
Warnings (shows only warning messages) 48
Nexys-3 FPGA Board (1) [6]
 Nexys-3 FPGA board features:
Xilinx Spartan-6 XC6LX16-CS324-3
Total of 48Mbytes of external memory
10/100 Ethernet port
micro USB port for power and programming
micro USB UART port
Type-A USB host port
VGA port
Four Pmod and one VHDC GPIO connectors
Eight slide switches, five push buttons and eight
LEDs, four-digit seven-segment display
100MHz fixed-frequency oscillator
[6] Nexys 3 FPGA Board Reference Manual, Digilent Inc., April 11, 2016. 49
Nexys-3 FPGA Board (2) [6]

[6] Nexys 3 FPGA Board Reference Manual, Digilent Inc., April 11, 2016. 50