MSc - Microprocessors

Dr. Konstantinos Tatas

[email protected]

1
Useful Information

 Instructor: Lecturer K. Tatas

– Office hours: TBA
– E-mail: [email protected]
– http://staff.fit.ac.cy/com.tk
 Lecture periods/week: 3
 Duration: 10 weeks
 ECTS: 7 (175 hours)

2
 Course Objectives
 By the end of the course students should be able
to:
– Evaluate the complex trade-offs involved in embedded
system design
– Write detailed embedded system requirements and
specification documents
– Write executable specifications using UML/SystemC
– Develop applications using ARM Developer Suite
– Write efficient ARM assembly and C programs in ARM and
Thumb mode
– Analyze program performance using traces
– Use code transformations to improve performance/code
size/power consumption.

3
 Course Outline (1/2)
 Week 1: Introduction to embedded systems – Embedded
microprocessor evolution – Design metrics and constraints
(performance, power, cost, time-to-market) and design optimization
challenges - Distributed and Real-time systems
 Week2: Key embedded system technologies – Integrated Circuit
technology – Microprocessor technology – CAD tool technology –
Sensor technology
 Week 3: Embedded system specification and modeling – Object-
oriented specification (UML/C++/SystemC) – Assignment 1
 Week 4: Computer Architecture – Instruction sets – RISC vs. CISC
– pipelining - The ARM microprocessor architecture - ARM assembly
– ARM mode – Thumb mode - ARM and Thumb instruction set -
ARM conditional execution
 Week 5: Processor I/O – Serial I/O – Busy/wait I/O – Interrupts –
Exceptions – Traps – ARM memory mapped I/O - Caches – Memory
Management Units – Protection Units – ARM cache and MMU –
Assignment 2
4
Course Outline (2/2)
 Week 6: Assignment 1
 Week 7: Programme design and analysis – DFGs –
CDFGs – Compilers – Assemblers – Linkers – Basic
compiler optimizations/code transformations –
Measuring programme speed – Trace-driven
performance analysis – Energy optimization –
programme size optimization
 Week 8: Code transformations – Loop unrolling –
loop merging – loop tiling – performance optimizing
transformations
 Week 9: Test
 Week 10: Assignment 2

5
Course Assessment

 Final exam: 40%

 Coursework: 60%
– Assignment 1: 15%
– Assignment 2: 15%
– Quizzes: 10%
– Test: 10%
– Lab exercises: 10%

6
References
 Books
– W. Wolf, “Computers as Components”
– W. Wolf, “High-Performance Embedded
Computing”
– H. Kopetz, “Real-Time Systems: Design Principles
for Distributed Embedded Applications”
– S. Furber, “ARM System-on-Chip Architecture”
– P. Panda, “Memory Issues in Embedded Systems-
on-Chip”
– F. Vahid and T. Givargis, “Embedded System
Design: A Unified Hardware/Software
Introduction”
– F. Catthoor, “Data Access and Storage Management
for Embedded Programmable Processors”

7
Microprocessors for
Embedded systems
 Computing systems are everywhere
 Most of us think of “desktop”
computers
– PC’s
– Laptops
– Mainframes
– Servers
 But there’s another type of computing
system
– Far more common... 8
 Embedded systems
overview
Embedded computing
Computers are in here...

systems and here...

– Computing systems embedded and even here...

within electronic devices

– Hard to define. Nearly any
computing system other than a
desktop computer
– Billions of units produced yearly, Lots more of these,

versus millions of desktop units

though they cost a lot
less each.

– Perhaps 50 per household and

per automobile 9
 A “short list” of embedded systems
Anti-lock brakes Modems
Auto-focus cameras MPEG decoders
Automatic teller Network cards
machines Network
Automatic toll systems switches/routers
Automatic transmission On-board navigation
Avionic systems Pagers
Battery chargers Photocopiers
Camcorders Point-of-sale systems
Cell phones Portable video games
Cell-phone base Printers
stations Satellite phones
Cordless phones Scanners
Cruise control Smart
Curbside check-in ovens/dishwashers
systems Speech recognizers
Digital cameras Stereo systems
Disk drives Teleconferencing
Electronic card readers systems
Electronic instruments Televisions
Electronic toys/games Temperature

And the list

Factory control controllers
Fax machines Theft tracking systems
Fingerprint identifiers TV set-top boxes

goes on and on
Home security systems VCR’s, DVD players
Life-support systems Video game consoles
Medical testing systems Video phones 10
Washers and dryers
Some common characteristics of
embedded systems

 Single-functioned
– Executes a single program, repeatedly
 Tightly-constrained
– Low cost, low power, small, fast, etc.
 Reactive and real-time
– Continually reacts to changes in the
system’s environment
– Must compute certain results in real-time
without delay 11
 An embedded system example –
Digital camera
Digital camera chip
CCD

CCD preprocessor Pixel coprocessor D2A

A2D

lens

JPEG codec Microcontroller Multiplier/Accum

DMA controller Display ctrl

Memory controller ISA bus interface UART LCD ctrl

 Single-functioned -- always a digital camera

 Tightly-constrained -- Low cost, low power, small, fast
 Reactive and real-time -- only to a small extent
12
Embedded Software Development
Requires as Much/More Design Effort Than
Hardware

13
A System-on-a-Chip:
Example

Courtesy: Philips

14
Design at a crossroad
System-on-a-Chip

Multi- 500 k Gates FPGA  Embedded applications

Analog
Spectral + 1 Gbit DRAM
RAM
where cost, performance,
Imager Preprocessing and energy are the real
issues!
64 SIMD Processor mC
Array + SRAM system  DSP and control intensive
+2 Gbit  Mixed-mode
Image Conditioning DRAM
Recog-  Combines programmable
100 GOPS
nition and application-specific
modules
 Software plays crucial role
15
Disciplines involved in
Embedded System Design
 Digital System Design
 Software Design
 Analog/Mixed-Signal/RF System Design
 Operating Systems
 Microprocessors/Computer Architecture
 Verification
 Testing
 etc
16
Languages traditionally used
in Embedded System Design
 Specification/modeling  Software design
– UML – C/C++
– SDL – Java
– C/C++ – Assembly
 Hardware design  Verification
– VHDL – VHDL/Verilog
– Verilog – SystemVerilog
– Tcl/tk
– Vera
17
Design challenge – optimizing
design metrics
 Obvious design goal:
– Construct an implementation with desired
functionality
 Key design challenge:
– Simultaneously optimize numerous design
metrics
 Design metric
– A measurable feature of a system’s
implementation
– Optimizing design metrics is a key 18
challenge
Design challenge –
optimizing design metrics
 Common metrics
– Unit cost: the monetary cost of manufacturing each
copy of the system, excluding NRE cost
– NRE cost (Non-Recurring Engineering
cost): The one-time monetary cost of designing the
system
– Size: the physical space required by the system
– Performance: the execution time or throughput of
the system
– Power: the amount of power consumed by the system
– Flexibility: the ability to change the functionality of
the system without incurring heavy NRE cost 19
Design challenge – optimizing
design metrics

 Common metrics (continued)

– Time-to-prototype: the time needed to
build a working version of the system
– Time-to-market: the time required to
develop a system to the point that it can be
released and sold to customers
– Maintainability: the ability to modify the
system after its initial release
– Correctness, safety, many more 20
 Design metric competition -- improving
one may worsen others
Power

 Expertise with both

Performance Size
software and hardware
is needed to optimize
design metrics
NRE cost – Not just a hardware
or software expert,
as is common
– A designer must be
CCD
Digital camera chip
comfortable with
various technologies
CCD preprocessor Pixel coprocessor D2A
A2D

in order to choose
lens

JPEG codec Microcontroller Multiplier/Accum

the best for a given
application and
DMA controller Display ctrl

constraints 21
Memory controller ISA bus interface UART LCD ctrl
 Time-to-market: a demanding
design metric
 Time required to
develop a product to
the point it can be sold
to customers
Revenues ($)

 Market window
– Period during which
the product would
have highest sales
Time (months)  Average time-to-
market constraint is
about 8 months
22
 Delays can be costly
 Losses due to delayed market entry

Peak revenue
 Simplified revenue model
Revenues ($)

Peak revenue – Product life = 2W, peak

from delayed
On-time entry at W
Market Market – Time of market entry
rise fall defines a triangle,
Delayed
representing market
penetration
D W 2W – Triangle area equals
On-time Delayed Time revenue
entry entry  Loss
– The difference between
the on-time and delayed
triangle areas 23
 Losses due to delayed market entry
(cont.)

 Area = 1/2 * base * height

Peak revenue
– On-time = 1/2 * 2W * W
Revenues ($)

Peak revenue – Delayed = 1/2 * (W-

from delayed
On-time entry D+W)*(W-D)
Market Market  Percentage revenue loss =
rise fall (D(3W-D)/2W2)*100%
Delayed
 Try some examples
– Lifetime 2W=52 wks, delay D=4 wks
D W 2W
– (4*(3*26 –4)/2*26^2) = 22%
On-time Delayed Time
entry entry
– Lifetime 2W=52 wks, delay D=10 wks
– (10*(3*26 –10)/2*26^2) = 50%
– Delays are costly!
24
The performance design metric

 Widely-used measure of system, widely-abused

– Clock frequency, instructions per second – not good
measures
– Digital camera example – a user cares about how fast it
processes images, not clock speed or instructions per
second
 Latency (response time)
– Time between task start and end
– e.g., Camera’s A and B process images in 0.25 seconds
 Throughput
– Tasks per second, e.g. Camera A processes 4 images per
second
– Throughput can be more than latency seems to imply due
to concurrency, e.g. Camera B may process 8 images per
second (by capturing a new image while previous image
is being stored).
 Speedup of B over S = B’s performance / A’s performance 25
– Throughput speedup = 8/4 = 2
Three key embedded system
technologies

 Technology
– A manner of accomplishing a task,
especially using technical processes,
methods, or knowledge
 Three key technologies for embedded
systems
– Processor technology
– IC technology
– Design technology 26
 Processor technology
 The architecture of the computation engine used to
implement a system’s desired functionality
 Processor does not have to be programmable
– “Processor” not equal to general-purpose processor
Controller Datapath Controller Datapath Controller Datapath
Control index
Control Register Control logic Registers
logic
logic and file and State total
State register register
Custom State
+
ALU register
General
IR PC ALU IR PC
Data Data
memory memory
Program Data Program memory
memory memory
Assembly code Assembly code
for: for:

total = 0 total = 0
for i =1 to … for i =1 to …
27
General-purpose (“software”) Application-specific Single-purpose (“hardware”)
 Processor technology

 Processors vary in their customization for the problem

at hand total = 0
for i = 1 to N loop
total += M[i]
end loop
Desired
functionality

General-purpose Application-specific Single-purpose

processor processor processor 28
 General-purpose
processors
Controller Datapath

 Programmable device used in a Control

logic and
Register

variety of applications State register

file

– Also known as “microprocessor”

General
 Features IR PC ALU

– Program memory
– General datapath with large Program memory Data
register file and general ALU memory

 User benefits Assembly code

for:

– Low time-to-market and NRE costs total = 0

for i =1 to …
– High flexibility
 “Pentium” the most well-known, but 29
there are hundreds of others
 Single-purpose
processors
Controller Datapath

 Digital circuit designed to Control logic index

execute exactly one program
total
– a.k.a. coprocessor, accelerator or State register
peripheral +

 Features
– Contains only the components Data
needed to execute a single memory
program
– No program memory
 Benefits
– Fast
– Low power 30

– Small size
 Application-specific
processors Controller Datapath

 Programmable processor Control

logic and
Registers

optimized for a particular class of State register

applications having common Custom

ALU
characteristics IR PC

– Compromise between general-purpose Data

and single-purpose processors Program memory memory

 Features
Assembly code
– Program memory for:

– Optimized datapath total = 0

for i =1 to …
– Special functional units
 Benefits
– Some flexibility, good performance, 31

size and power

 IC technology
 The manner in which a digital (gate-level)
implementation is mapped onto an IC
– IC: Integrated circuit, or “chip”
– IC technologies differ in their customization to a
design
– IC’s consist of numerous layers (perhaps 10 or
more)
 IC technologies differ with respect to who builds
each layer and when

gate

oxide
IC package IC
source channel drain
32
Silicon substrate
 IC technology Design
Approaches
IC Technology Implementation Approaches

Custom Semicustom

Cell-based Array-based

Standard Cells Pre-diffused Pre-wired

Macro Cells
Compiled Cells (Gate Arrays) (FPGA's)

33
 Full-custom design

 All layers are optimized for an embedded

system’s particular digital implementation
– Placing transistors
– Sizing transistors
– Routing wires
 Benefits
– Excellent performance, small size, low power
 Drawbacks
– High NRE cost (e.g., $300k), long time-to-market
34
The Custom Approach
Intel 4004

35
Courtesy Intel
Transition to Automation and Regular
Structures

Intel 4004 (‘71)

Intel 8080 Intel 8085

36
Intel 8286 Courtesy Intel Intel 8486
37
 IC technology Design
Approaches
IC Technology Implementation Approaches

Custom Semicustom

Cell-based Array-based

Standard Cells Pre-diffused Pre-wired

Macro Cells
Compiled Cells (Gate Arrays) (FPGA's)

38
Semi-custom

 Lower layers are fully or partially built

– Designers are left with routing of wires
and maybe placing some blocks
 Benefits
– Good performance, good size, less NRE
cost than a full-custom implementation
(perhaps $10k to $100k)
 Drawbacks
– Still require weeks to months to develop 39
Cell-based Design (or
standard cells)

Routing channel
requirements are
reduced by presence
of more interconnect
layers

40
Standard Cell — Example

[Brodersen92]
41
Standard Cell - Example

3-input NAND cell

(from ST Microelectronics):
C = Load capacitance
T = input rise/fall time
42
 IC technology Design
Approaches
IC Technology Implementation Approaches

Custom Semicustom

Cell-based Array-based

Standard Cells Pre-diffused Pre-wired

Macro Cells
Compiled Cells (Gate Arrays) (FPGA's)

43
Programmable Logic Devices

 All layers (diffusion, polysilicon, [multi-]

metal) may exist
– Designers can purchase an IC
– Connections on the IC are either created or
destroyed to implement desired functionality
– Field-Programmable Gate Array (FPGA) and
recently Gate Arrays are very popular
 Benefits
– Low NRE costs, almost instant IC availability
 Drawbacks
– Bigger, expensive (perhaps $30 per unit), power
hungry, slower
44
Gate Array — Sea-of-
gates
polysilicon

VD D

metal
rows of Uncommited
uncommitted possible
cells GND contact Cell

In1 In2 In3 In4

routing
channel Committed
Cell
(4-input NOR)
Out

45
Sea-of-gate Primitive Cells

Oxide-isolation

PMOS

PMOS

NMOS

NMOS
NMOS

Using oxide-isolation Using gate-isolation 46

 Sea-of-gates

Random Logic

Memory
Subsystem

LSI Logic LEA300K

(0.6 mm CMOS)47
 Prewired Arrays
Classification of prewired arrays (or field-
programmable devices):
 Based on Programming Technique
– Fuse-based (program-once)
– Non-volatile EPROM based
– RAM based
 Programmable Logic Style
– Array-Based
– Look-up Table
 Programmable Interconnect Style
– Channel-routing
48
– Mesh networks
Altera MAX

49

From Smith97
 Altera MAX Interconnect
Architecture
column channel row channel

t PIA

LAB1 LAB2

LAB

PIA

t PIA
LAB6

Array-based Mesh-based
50
(MAX 3000-7000) (MAX 9000)
LUT-Based Logic Cell
4
C1....C4

xx xxxx xxxx xxxx

D4 Bits xxxx
Logic control
D3 xx xx
function xx
xx x xx x
D2 of xx
xxx
D1
Logic xx xx
functionx x
x
of x x
F4 xxx
Bits xxxx
F3 Logic xx control xx
function xx
xx x xx x
F2 of xx
xxx
F1
xx xx
x
xxxxx x
H x
P
Multiplexer Controlled
by Configuration Program 51
Xilinx 4000 Series
Array-Based Programmable
Wiring
Interconnect
Point
M

Programmed interconnection Input/output pin

Cell

Horizontal
tracks

52
Vertical tracks
Transistor Implementation of
Mesh

53

Courtesy Dehon and Wawrzyniek

RAM-based FPGA

Xilinx XC4000ex
54
Design Technology
 The manner in which we convert our concept
of desired system functionality into an
implementation
Compilation/ Libraries/ Test/
Synthesis IP Verification

System System Hw/Sw/ Model simulat./

Compilation/Synthesis: specification synthesis OS checkers
Automates exploration and
insertion of implementation
details for lower level.
Behavioral Behavior Cores Hw-Sw
specification synthesis cosimulators
Libraries/IP: Incorporates pre-
designed implementation from
lower abstraction level into
higher level. RT RT RT HDL simulators
specification synthesis components

Test/Verification: Ensures
correct functionality at each
level, thus reducing costly Logic Logic Gates/ Gate
iterations between levels. specification synthesis Cells simulators

To final implementation
55
 The co-design ladder
 In the past: Sequential program code (e.g., C, VHDL)

– Hardware and software Compilers

Behavioral synthesis
(1990's)
design technologies (1960's,1970's)

were very different Register transfers

Assembly instructions RT synthesis
– Recent maturation of (1980's, 1990's)

synthesis enables a
Assemblers, linkers
(1950's, 1960's) Logic equations / FSM's
unified view of Logic synthesis
(1970's, 1980's)
hardware and software Machine instructions
Logic gates
 Hardware/software
“codesign” Microprocessor plus
Implementation
VLSI, ASIC, or PLD
program bits: “software” implementation: “hardware”

The choice of hardware versus software for a particular function is simply a tradeoff among various
design metrics, like performance, power, size, NRE cost, and especially flexibility; there is no
fundamental difference between what hardware or software can implement.

56
 Independence of processor and IC
technologies
 Basic tradeoff
– General vs. custom
– With respect to processor technology or IC
technology
– The two technologies are independent
General- Single-
purpose ASIP purpose
General, processor processor Customized,
providing improved: providing improved:

Flexibility Power efficiency

Maintainability Performance
NRE cost Size
Time- to-prototype Cost (high volume)
Time-to-market
Cost (low volume)

PLD Semi-custom Full-custom 57

Design Decision Trade-offs

58
Generalised Design Flow

59
 Architecture ReUse
 Silicon System Platform
– Flexible architecture for hardware and software
– Specific (programmable) components
– Network architecture
– Software modules
– Rules and guidelines for design of HW and SW
 Has been successful in PC’s
– Dominance of a few players who specify and control architecture
 Application-domain specific (difference in constraints)
– Speed (compute power)
– Dissipation
– Costs
– Real / non-real time data

60
Platform-Based Design
“Only the consumer gets freedom of choice;
designers need freedom from choice”
(Orfali, et al, 1996, p.522)
 A platform is a restriction on the space of possible implementation
choices, providing a well-defined abstraction of the underlying
technology for the application developer
 New platforms will be defined at the architecture-micro-architecture
boundary
 They will be component-based, and will provide a range of choices
from structured-custom to fully programmable implementations
 Key to such approaches is the representation of communication in
the platform model

61
Source:R.Newton
Platform-based Design –
System-on-Chip
 Use of predefined Intellectual Property (IP)
 A platform-based system consists of a RISC
processor, memories, busses and a common
language
 Platform-based design poses the problem of
partitioning a solution between hardware
(HDL) and software (programming
processors)

62
Platforms Enable Simplified SoC
Design
Core  Customer demands
Near Peripherals
– Fast turn-around time
– Easy access to pre-qualified
building blocks
– Web enabled
 Design technology
– Core platforms
– ‘Big’ IP
– Emerging SoC bus standards
– Embedded software
Far Peripherals – HW/SW co-verification 63
And Automation of IP Selection
& Integration

64
Heterogeneous Programmable
Platforms FPGA Fabric

Embedded memories
Embedded PowerPc

Hardwired multipliers

Xilinx Vertex-II Pro

65
High-speed I/O
Xilinx’s products

66
Xilinx’s products

67
 Comparison of CMOS design
methods
Design NRE Unit Cost Power Complexity Time-to- Performance Flexibility
Method Dissipation of Market
Implement
ation
μProcessor low medium high low low low high
/DSP

PLA low medium medium low low medium low

FPGA low high medium medium medium medium medium

Gate/Array medium medium low medium medium medium medium

Cell Based high low low high high high low

Custom high low low high high Very high low

Design

Platform high Low/mediu low high Medium/l high medium

Based m ow
68
 Energy Efficiency (in MOPS/mW)

Hardwired custom

None
100-1000
Choices

Configurable/Parameterizable
10-100

flexible
Domain-specific processor

Somewhat
(e.g. DSP)
1-10

Embedded microprocessor
Fully
flexible
0.1-1

Flexibility
Impact of Implementation

69
(or application scope)
Design Economics (1)

 The selling price of an IC Stotal=Ctotal/(1-m),

Ctotal is manufacturing cost for a single IC,
m desired profit margin
 Costs for produce an IC
– Non-recurring engineering costs (NREs)
– Recurring engineering costs
– Fixed costs

70
Design Economics (2)

 Non-recurring engineering costs

(NREs)
– Engineering design cost
– Prototype manufacturing cost
 Recurring costs
– Process
– Package
– Test
71
 NRE and unit cost metrics

 Costs:
– Unit cost: the monetary cost of manufacturing each copy
of the system, excluding NRE cost
– NRE cost (Non-Recurring Engineering cost): The one-time
monetary cost of designing the system
– total cost = NRE cost + unit cost * # of units
– per-product cost = total cost / # of units
= (NRE cost / # of units) + unit cost
• Example
– NRE=$2000, unit=$100
– For 10 units
– total cost = $2000 + 10*$100 = $3000
– per-product cost = $2000/10 + $100 = $300
72
Amortizing NRE cost over the units results in an
additional $200 per unit
 NRE and unit cost metrics
 Compare technologies by costs -- best depends on
quantity
– Technology A: NRE=$2,000, unit=$100
– Technology B: NRE=$30,000, unit=$30
– Technology C: NRE=$100,000, unit=$2
$200,000 $200
A A
B B
$160,000 $160
C C
tota l c ost (x1000)

p er p rod uc t c ost
$120,000 $120

$80,000 $80

$40,000 $40

$0 $0
0 800 1600 2400 0 800 1600 2400
Numb er of units (volume) Numb er of units (volume)

• But, must also consider time-to-market 73

Wafer and die cost

Die yield: number of good dies/total number of dies

74
Example
 Assuming:
– 20 engineers are employed full-time for a year
with a $50,000/year average salary
– Additional 200,000 overhead costs of which
100,000 for total testing
– A wafer cost of $200 per wafer
– A $2 packaging cost per chip
– 10 dies/wafer
– 70% die yield
– 98% final test yield
– A market for 100,000 items
 Calculate the minimum shelf price of the
chip 75
 Design productivity exponential
increase
100,000

10,000

(K) Trans./Staff – Mo.

1,000

Productivity
100

10

0.1

0.01

2005
2001
1993

2003
1987
1983

1985

1991
1989

1999
1997
1995

2007

2009
 Exponential increase over the past few
decades
76
 The growing design-
productivity gap
Moore’s Law: Design Productivity Crisis (SRC 1997)
Standard cell density and speed Potential Design Complexity and Designer Productivity
10,000 10,000 100,000,000
Equivalent Added Complexity

Productivity (K) Trans./Staff – Mo.

Logic Transistor per Chip (M)
1,000 10,000
Clock
Logic Tr./Chip
Density (Kgates/mm2)

Gates
100
ASIC clock (MHz)

Tr./S.M. 1,000

10 100

1,000
1 10

x x
0.1 1
xx
xx x
x
0.01 0.1

100 0.001 0.01

Return volume * (chip ASP  chip unit cost )

ROI   77

Investment chip developmen t cost

Design productivity gap
 1981 leading edge chip required 100
designer months
– 10,000 transistors / 100
transistors/month
 2002 leading edge chip requires 30,000
designer months
– 150,000,000 / 5000 transistors/month
 Designer cost increase from $1M to $300M

 While designer productivity has grown at an

impressive rate over the past decades, the
rate of improvement has not kept pace with
chip capacity
78
 The mythical man-month
 The situation is even worse than the productivity gap indicates
 In theory, adding designers to team reduces project completion time
 In reality, productivity per designer decreases due to complexities of team
management and communication
 In the software community, known as “the mythical man-month” (Brooks 1975)
 At some point, can actually lengthen project completion time! (“Too many
cooks”)
Team
 1M transistors, 1 60000
16
15
16
designer=5000 50000 18
19
trans/month
40000
 Each additional 24 23
30000
designer reduces for
Months until completion
100 trans/month 20000
43
 So 2 designers produce10000 Individual
4900 trans/month each
79
0 10 20 30 40
Number of designers
Summary
 Embedded systems are everywhere
 Key challenge: optimization of design metrics
– Design metrics compete with one another
 A unified view of hardware and software is
necessary to improve productivity
 Three key technologies
– Processor: general-purpose, application-specific, single-
purpose
– IC: Full-custom, semi-custom, PLD
– Design: Compilation/synthesis, libraries/IP, test/verification

80
Real-time and
distributed systems
Dr. Konstantinos Tatas

81
What is real-time? Is there
any other kind?
 A real-time computer system is a
computer system where the
correctness of the system behavior
depends not only on the logical results
of the computations, but also on the
physical time when these results are
produced.
 By system behavior we mean the
sequence of outputs in time of a 82
Real-time means reactive
 A real-time computer system must react to stimuli
from its environment
 The instant when a result must be produced is
called a deadline.
 If a result has utility even after the deadline has
passed, the deadline is classified as soft, otherwise
it is firm.
 If severe consequences could result if a firm
deadline is missed, the deadline is called hard.
 Example: Consider a traffic signal at a road before a
railway crossing. If the traffic signal does not
change to red before the train arrives, an accident
could result. 83
Reliability
 The Reliability R(t) of a system is the probability that a system
will provide the specified service until time t, given that the
system was operational at the beginning (t-t0)
 The probability that a system will fail in a given interval of
time is expressed by the failure rate, measured in FITs (Failure
In Time).
 A failure rate of 1 FIT means that the mean time to a failure
(MTTF) of a device is 10^9 h, i.e., one failure occurs in about
115,000 years.
 If a system has a constant failure rate of λ failures/h, then the
reliability at time t is given by
 R(t)= exp(-λ(t-to))
 MTTF = 1/λ

84
Example

 What must be the system failure rate

so that 99% of the systems in the field
work reliably for the first 100,000
hours?

85
Safety

86
Maintainability

87
Name some hard, firm and
soft deadline embedded
systems

88
Example
 an automotive company produces 2,000,000 electronic engine
controllers of a special type.
 The following design alternatives are discussed
 (a) Construct the engine control unit as a single SRU with the
application software in Read Only Memory (ROM).The production
cost of such a unit is $250. In case of an error, the complete unit
has to be replaced.
 (b) Construct the engine control unit such that the software is
contained in a ROM that is placed on a socket and can be replaced
in case of a software error. The production cost of the unit without
the ROM is $248. The cost of the ROM is $5.
 (c) Construct the engine control unit as a single SRU where the
software is loaded in a Flash EPROM that can be reloaded. The
production cost of such a unit is $255.
 The labor cost of repair is assumed to be $50 for each vehicle. (It is
assumed to be the same for each one of the three alternatives).
 Calculate the cost of a software error for each one of the three
alternative designs if 300,000 cars have to be recalled because of
the software error (example in Sect. 1.6.1).
 Which one is the lowest cost alternative if only 1,000 cars are
affected by a recall? 89
Distributed RT system
model
 From the POV of an outside observer, a real-time
(RT) system can be decomposed into three
communicating subsystems:
– a controlled object (the physical subsystem, the behavior
of which is governed by the laws of physics),
– a “distributed” computer subsystem (the cyber system, the
behavior of which is governed by the programs that are
executed on digital computers)
– a human user or operator
 The distributed computer system consists of
computational nodes that interact by the exchange
of messages.
 A computational node can host one or more
computational components.
90
Event-Triggered Control
Versus Time-Triggered
Control

91
92