Analog and Digital VLSI Design: Lecture 8: MOS Operation
Analog and Digital VLSI Design: Lecture 8: MOS Operation
For NMOS
Assert high switch
VG (A) 0, NMOS is on, else it will be off (open circuit)
it may be written as: y x. A
MOS Capitance
A
Vg < 0 -- C
t
MOS ox
Polysilicon Gate ox
Accumulation
MOS as a Capacitor
For 0<V <V , electrons (minority) are attracted,
G T
For an nMOS: I f (V ,V )
ds gs ds
Charge is carried by e-
()
=
nMOS I-V
6
2.5
5
4
2
= 0 V <
3
2 1.5
Cut off 1
1
0
0 0.5 1 1.5 2 2.5
= V >
2 V <
Linear, Resistive
2 V >
= V >
2
Saturation
nMOS I-V
If Vds << (Vgs -Vt )
Velocity saturation
The drift velocity saturates at some electric field (Ec)
Non Ideal Effects
Mobility Degradation
- + - +
G
S D
- - n+- -- -- -- - -- --- - -- -- -- -- -- -- - - - - - - - n+ - -
+ +
+ + p- Body + - + +
+ + - + + -
+ + + + - + - - + + + +
+ +
- -
> eff
Non Ideal Effects
Tunneling Leakage gate current
G
n+ - - - - - - - - - - - - - -- n+
Non Ideal Effects
Body effect
= 0 + ( + )
Geometry Dependence
Mismatch between assumed and actual sizes
Parasitics
CKV
Thank You