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Pipelining

The document discusses pipelining in computer processors. It describes how pipelining allows overlapping execution of instructions to improve throughput. It identifies different types of hazards that can cause the pipeline to stall, such as data hazards when instructions depend on previous results, instruction hazards from cache misses or branches, and structural hazards from limited hardware resources. The document outlines techniques used in hardware and software to minimize the impact of hazards on performance, such as forwarding, branch prediction, and compiler optimizations.

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660 views

Pipelining

The document discusses pipelining in computer processors. It describes how pipelining allows overlapping execution of instructions to improve throughput. It identifies different types of hazards that can cause the pipeline to stall, such as data hazards when instructions depend on previous results, instruction hazards from cache misses or branches, and structural hazards from limited hardware resources. The document outlines techniques used in hardware and software to minimize the impact of hazards on performance, such as forwarding, branch prediction, and compiler optimizations.

Uploaded by

mail2murutech
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PPT, PDF, TXT or read online on Scribd
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Pipelining

CS1251
Computer Organization
Carl Hamacher

Department of Information
10/5/2017 Technology 1
Pipelining
I1 I2 I3

F1 E1 F2 E2 F3 E3

Sequential Execution

I1 F1 E1

I2 F2 E2

I3 F3 E3

Pipelined Execution

10/5/2017 Department of Information Technology 2


Hardware Organization

Interstage Buffer
B1

Instruction
Execution
Fetch
Unit
Unit

10/5/2017 Department of Information Technology 3


Four State Pipeline
Fetch (F)
Read the instruction from memory
Decode (D)
Decode the instruction and fetch the source operand(s)
Execute (E)
Perform the operation specified by the instruction
Write (W)
Store the result in the destination location

10/5/2017 Department of Information Technology 4


Four Stage Pipeline

10/5/2017 Department of Information Technology 5


Hardware Organization

10/5/2017 Department of Information Technology 6


Data Hazard
Pipeline stalled
Source or destination operands not available at time
expected in the pipeline
Execution operation taking more than one clock
cycle

10/5/2017 Department of Information Technology 7


Data Hazard

10/5/2017 Department of Information Technology 8


Data Dependency

10/5/2017 Department of Information Technology 9


Operand Forwarding

10/5/2017 Department of Information Technology 10


Operand Forwarding

10/5/2017 Department of Information Technology 11


Handling Data Hazards in SW
Compiler detect data dependencies and deal with them
Insert NOPs
Attempt to reorder instructions to perform useful tasks in
NOP slots
Side effects
Instruction changes contents of a register other than the
named destination
Autoincrement/autodecrement addressing modes
Condition code flags
Give rise to multiple dependencies
Should be minimized

10/5/2017 Department of Information Technology 12


Instruction Hazards
Pipeline stalled
Delay in the availability of an instruction
Cache miss
Branch instructions

10/5/2017 Department of Information Technology 13


Instruction Hazard

10/5/2017 Department of Information Technology 14


Instruction Queue and Prefetch

10/5/2017 Department of Information Technology 15


Branch Penalty

10/5/2017 Department of Information Technology 16


Branch Prediction
Attempt to predict whether or not a particular branch
will be taken
Speculative execution
Continue to execute until outcome of branch evaluated
No processor registers or memory can be updated until
branch outcome is confirmed

10/5/2017 Department of Information Technology 17


Branch Prediction
Static Branch Prediction
Some branch instructions predicted as taken and others
as not taken
End or program loop
Beginning of program loop
Hardware or compiler
Dynamic Branch Prediction
Based on execution history

10/5/2017 Department of Information Technology 18


Structural Hazard
Two instructions require use of a given hardware
resource at the same time
Access to memory
Separate instruction and data caches
Access to register file
Multiple port register file
In general avoided by providing sufficient hardware
resources on the processor chip

10/5/2017 Department of Information Technology 19


Structural Hazard

10/5/2017 Department of Information Technology 20


Summary
Pipelining does not result in individual instructions
being executed faster
Throughput increases
Rate at which instruction execution is completed
Important goal in designing processors is to identify
all hazards that may cause the pipeline to stall
Find ways to minimize their impact

10/5/2017 Department of Information Technology 21


Questions?

10/5/2017 Department of Information Technology 22

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