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6-Delay-Fault Testing Tutorial

This document provides an overview of delay fault testing techniques. It first reviews common fault models including delay faults, which occur when an I/O path between clocked elements has excessive delay. It then discusses different types of delay faults like transition faults and path delay faults. The document outlines robust and non-robust path delay testing methods. It provides examples of delay fault testing techniques like broadside testing and skewed-load testing. Finally, it discusses advanced techniques like segment delay fault testing.

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Adhi Suruli
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© © All Rights Reserved
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Download as PPT, PDF, TXT or read online on Scribd
340 views

6-Delay-Fault Testing Tutorial

This document provides an overview of delay fault testing techniques. It first reviews common fault models including delay faults, which occur when an I/O path between clocked elements has excessive delay. It then discusses different types of delay faults like transition faults and path delay faults. The document outlines robust and non-robust path delay testing methods. It provides examples of delay fault testing techniques like broadside testing and skewed-load testing. Finally, it discusses advanced techniques like segment delay fault testing.

Uploaded by

Adhi Suruli
Copyright
© © All Rights Reserved
Available Formats
Download as PPT, PDF, TXT or read online on Scribd
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Delay-Fault Testing Tutorial

Acknowledgement: This presentation is adapted from


Professor Janak Patels tutorial on the same topic available
on the web at:
http://courses.ece.uiuc.edu/ece543/docs/DelayFault_6_per_page.pdf
Outline
Common Fault Models (Review)
Defects and Delay Faults
Delay Fault Models
Transition Faults
Path Delay Faults
Robust Path Test
Non-robust Path Test

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Common Fault Models
Fault Model Definition
Stuck-at Fault (SAF) Logic line stuck at 0 or 1
(can be single or multiple)
Bridging Signals x and y become
AND(x,y) or OR(x,y)
Stuck-open Signal x stuck in some
previous state
Delay An I/O path between clocked
elements has excessive delay
Coupling Signals x and y become F(x,y)
Pattern Interference Signals interact in space & time

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Only if no other path delay is increased.

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Exercise
Consider the 4-Nand implementation of the
XOR gate in the previous slide. There are
six I/O paths hence 12 path delay faults. For
each of these faults, determine if it is
robustly testable, only non-robustly testable
or not testable (functionally redundant).
Provide justification for your answers.

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Broadside is also called launch-off-capture test.
Skewed-Load is also called launch-off-shift test.

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Timing for
launch-off-
capture
Transition-delay
fault testing

IC: Initialization Clock


LC: Launch Clock
CC: Capture Clock
SEN: Scan Enable

This figure is borrowed from the paper, Ahmed et al., ITC-2005, Paper 11.1
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Timing for
launch-off-shift
Transition-
delay fault
testing

IC: Initialization Clock


LC: Launch Clock
CC: Capture Clock
SEN: Scan Enable

Delay
This figure is borrowed from FaultAhmed
the paper, Testing TuITC-2005, Paper 11.131
et al.,
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(See Prof. Patels website for details on Segment Test)
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