MICROPROCESSOR
MOTOROLA 6800
By
Anupam
E. No. - 15122003
MOTOROLA 6800
History of Motorola 6800
The6800("sixty-eight-hundred")wasan8-bitmicroprocessor
designedandfirstmanufacturedbyMotorolain1974.
The6800hasa16-bitaddressbusthatcoulddirectlyaccess64
KBofmemoryandan8-bitbi-directionaldatabus.
Ithas72instructionswithsevenaddressingmodesforatotalof
197opcodes.TheoriginalMC6800couldhaveaclockfrequency
ofupto1MHz.Laterversionshadamaximumclockfrequency
of2MHz.
SHORT DESCRIPTION OF PIN DIAGRAM
6800 ARCHITECTURE
REGISTER SET AND PROGRAMMERS MODEL
The6800hassixinternallyaccessibleregisters.
Thesearetwo8-bitaccumulatorsorgeneralpurpose
register(AandB),
three16-bitregistersPC,SP,andIndexregister-X)
andan8-bitconditioncodeorstatusregisterwhichhas
6flagsintotal.
A 8 bit accumulators,
general purpose
B registers
Program Counter - PC
Stack Pointer - SP 16 bit registers
Index Register - X
H I N Z V C
8 bit status register
The Accumulators A and B:
Eachstoresandmanipulatesone8-bitwordunderprogramcontrol.
The Index register - X
Isa2-byteregister.Itholdsmemoryaddresseswhenusingindexed-addressingmode
instructions.
The Program Counter - PC
Isa2-byteregisterwhichcontainstheaddressofthenextbyteoftheinstructiontobefetched
frommemory(instructionscanbefromoneto3bytesinlength).Whenthecurrentvalueof
theprogramcounterisplacedontheaddressbus,thePCisupdatedtothevalueofthenext
instructionforexecution.
Stack pointer - SP
A2-byteregisterwhichholdsthestartingaddressofsequentialmemory
locationsinRAMwherethecontentsoftheCPUregistersmaybestored
andretrieved.The6800usesRAMforitsstack.
Status Register or Condition Codes Register
Thisfinalregistercontainssixflagswhicharesetorclearedinresponseto
howtheprogramexecutes.Theseflagsare:
Condition Code Register: Itshowstheconditionsoccursasa
resultofanArithmeticLogicUnit
Bit0:carryfrombit7ofanarithmeticoperation(C)
Bit1:Overflowflag(V)
Bit2:Zeroflag(Z)
Bit3:Negativeflag(N)
Bit4:InterruptMask(I)
Bit5:Halfcarryfrombit3ofanarithmeticoperation(H)
Bit6:Unused
Bit7:Unused
ThesebitsoftheConditionCodeRegisterareusedastestable
conditionsfortheconditionalbranchinstructions.Bit4ofthe
CCRistheinterruptmaskbit(I).Theunusedbitsofthe
ConditionCodeRegister(bit6andbit7)are1.
ADDRESSING MODES
The6800usesa16-bitaddressbusallowingaccessto65,5368-
bitwordswithinmemory.The16-bitaddresscanbesplitintoa
mostsignificant(MS)byte,thefirst8-bitsoftheaddressandthe
LeastSignificant(LS)bytethesecond8-bits.ForInputOutput
I/OaportionofmemoryspaceisusedtoaccessI/Oports.
Therearesevenaddressingmodesavailabletoa6800
programmer.
Accumulator Addressing
Inaccumulatoraddressing,eitheraccumulatorAoraccumulatorBis
specified.Theseare1-byteinstructions.
Ex: ABA addsthecontentsofaccumulatorsandstorestheresultin
accumulatorA
Immediate Addressing
Inimmediateaddressing,operandislocatedimmediatelyaftertheopcode
inthesecondbyteoftheinstructioninprogrammemory(exceptLDSand
LDXwheretheoperandisinthesecondandthirdbytesofthe
instruction).Theseare2-byteor3-byteinstructions.
Ex: LDAA #25H loadsthenumber(25)HintoaccumulatorA
Direct Addressing
Indirectaddressing,theaddressoftheoperandiscontainedinthesecond
byteoftheinstruction.Directaddressingallowstheusertodirectly
addressthelowest256bytesofthememory,i.e,locations0through255.
Enhancedexecutiontimesareachievedbystoringdataintheselocations.
Theseare2-byteinstructions.
Ex: LDAA 25H loadsthecontentsofthememoryaddress(25)Hinto
accumulatorA
Extended Addressing
Inextendedaddressing,theaddresscontainedinthesecondbyteof
theinstructionisusedasthehighereightbitsoftheaddressofthe
operand.Thethirdbyteoftheinstructionisusedasthelowereight
bitsoftheaddressfortheoperand.Thisisanabsoluteaddressin
thememory.Theseare3-byteinstructions.
Ex: LDAA 1000H loadsthecontentsofthememoryaddress
(1000)HintoaccumulatorA
Indexed Addressing
Inindexedaddressing,theaddresscontainedinthesecondbyteof
theinstructionisaddedtotheindexregisterslowesteightbits.
Thecarryisthenaddedtothehigherordereightbitsoftheindex
register.Thisresultisthenusedtoaddressmemory.Themodified
addressisheldinatemporaryaddressregistersothereisnochange
totheindexregister.Theseare2-byteinstructions.
Ex: LDX #1000H
LDAA 10H,X
Initially,LDX#1000Hinstructionloads1000Htotheindexregister
(X)usingimmediateaddressing.ThenLDAA10H,Xinstruction,
usingindexedaddressing,loadsthecontentsofmemoryaddress
(10)H+X=1010HintoaccumulatorA.
Implied (Inherent) Addressing
Intheimpliedaddressingmode,theinstructiongivestheaddress
inherently(i.e,stackpointer,indexregister,etc.).Inherent
instructionsareusedwhennooperandsneedtobefetched.These
are1-byteinstructions.
Ex: INX increasesthecontentsoftheIndexregisterbyone.The
addressinformationis"inherent"intheinstructionitself.
INCA increasesthecontentsoftheaccumulatorAbyone.
DECB decreasesthecontentsoftheaccumulatorBbyone.
Relative Addressing
Therelativeaddressingmodeisusedwithmostofthebranching
instructionsonthe6802microprocessor.Thefirstbyteofthe
instructionistheopcode.Thesecondbyteoftheinstructionis
calledtheoffset.Theoffsetisinterpretedasasigned 7-bit number.
IftheMSB(mostsignificantbit)oftheoffsetis0,thenumberis
positive,whichindicatesaforwardbranch.IftheMSBoftheoffset
is1,thenumberisnegative,whichindicatesabackwardbranch.
Thisallowstheusertoaddressdatainarangeof-126to+129
bytesofthepresentinstruction.Theseare2-byteinstructions.
Ex: PC Hex Label Instruction
00092004BRA0FH
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