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Bitslicing Using Small-Scale Hierarchical Floorplanning: Evan Vaughan

Evan Vaughan has been exploring using hierarchical floorplanning to implement a bitsliced datapath design in Encounter. Originally, a flat design approach was too time consuming and unsuccessful. The new approach uses hierarchical design methodologies to break the design into manageable blocks and floorplan the individual bit modules as fences within the core region. Specifying modules as fences allows for placement of standard cells within the defined regions and prevents cells from moving outside those areas during optimization. This hierarchical floorplanning approach with fenced modules has proven easier to implement and integrate into the design flow compared to earlier hacks, and allows the bitslice structure to be preserved during optimization.

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Æshok IncreĐible King
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42 views

Bitslicing Using Small-Scale Hierarchical Floorplanning: Evan Vaughan

Evan Vaughan has been exploring using hierarchical floorplanning to implement a bitsliced datapath design in Encounter. Originally, a flat design approach was too time consuming and unsuccessful. The new approach uses hierarchical design methodologies to break the design into manageable blocks and floorplan the individual bit modules as fences within the core region. Specifying modules as fences allows for placement of standard cells within the defined regions and prevents cells from moving outside those areas during optimization. This hierarchical floorplanning approach with fenced modules has proven easier to implement and integrate into the design flow compared to earlier hacks, and allows the bitslice structure to be preserved during optimization.

Uploaded by

Æshok IncreĐible King
Copyright
© © All Rights Reserved
Available Formats
Download as PPTX, PDF, TXT or read online on Scribd
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Bitslicing using Small-scale

Hierarchical Floorplanning
Evan Vaughan

Review
Get RTL Compilier and SoC Encounter to
place & route a bitsliced datapath
Began by modifying/reducing libraries

Modify>synthesize>P&R

Very time consuming and no good results.

Since the last time

Original approach involved far too much


custom design
Abandoned that.

Focus has shifted to floorplanning


Use hierarchical design methodologies to
floorplan

Hierarchical Design

Meant for large-scale designs


By default, Encounter only makes it available for
larger designs

Breaks design into manageable pieces when


floorplanning
Allows for parallel design of blocks

Approach

First must make a hierarchical design


Original Kogge-Stone verilog completely flat

Modified verilog to
make overall
design hierarchical

Synthesis Results
Flat Design

Hierarchical
Design

Place & Route

Hierarchical design yields no difference in


P&R

Hierarchical Floorplanning
Uses partitions, modules, groups, fences,
etc
Fence allows user to define spaces where
standard cells will be placed

Can specify modules as fences

Specify each bit module as a fence


Place fences in core as bitslices
Place cells in fences

Encounter wasnt showing my bits as


modules

Modules

Black Box Flow


Defining black boxes creates instances of
the modules
Can place modules by hand then place
black boxes (Place>Standard Cells)
Remove black boxes (unspecifyBlackBox
keepPtn)

Removes black boxes but leaves fence behind


Can then place standard cells within module
fences.

Placement

Problems

Kind of a hack
Cant unspecifyBlackBox from GUI
Multiple placements

Works fine as script but cumbersome in the


GUI
Can ignore Black Box flow and directly
specify fences in a script or in terminal

Still no way for GUI-based flow


Fences do not show up in floorplan view

GUI-based Flow

By default, Encounter requires >100 cells


for a module to be displayed after import.
Design>Preferences>Display Min. Floorplan
Module Size to change this.
Alternatively setPreference MinFPModuleSize 0
in a script/terminal

Can easily place & resize modules into the


core area
Define them as fences
Place standard cells

Scripting
Very easily implemented as a script
Fences prevent cells from moving outside of
assigned rows

Optimization can be run without destroying


bitslice

Easily integrated into any flow

Results

Final Layout (Preoptimization)

Post-optimization (Timing)

Final Layout (Post-optimization)

What Ive Learned

No previous ASIC design

Scripting
Synthesis
Place & Route
Verilog

Hierarchical Design methodologies

Questions?

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