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IO Interfacing

This document discusses different methods of interfacing I/O devices with microprocessors, including parallel and serial I/O. It describes memory mapped I/O and I/O mapped I/O, noting that memory mapped I/O treats I/O devices as memory locations while I/O mapped I/O uses port numbers. Output devices require external latching to hold data. Interfacing input devices decodes the address and IORD signal to enable a tri-state buffer connecting the device to the data bus.

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112 views10 pages

IO Interfacing

This document discusses different methods of interfacing I/O devices with microprocessors, including parallel and serial I/O. It describes memory mapped I/O and I/O mapped I/O, noting that memory mapped I/O treats I/O devices as memory locations while I/O mapped I/O uses port numbers. Output devices require external latching to hold data. Interfacing input devices decodes the address and IORD signal to enable a tri-state buffer connecting the device to the data bus.

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Axe Axe
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© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Interfacing I/O Devices

Using I/O devices data can be


transferred between the
microprocessor and the outside
world.
This can be done in groups of 8 bits
using the entire data bus. This is
called parallel I/O.
The other method is serial I/O where
one bit is transferred at a time using
the SID and SOD pins on the
Microprocessor.
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Types of Parallel Interface


There are two ways to interface 8085 with I/O
devices in parallel data transfer mode:
Memory Mapped IO
IO Mapped IO

Memory Mapped IO
It considers them like any other memory
location.
They are assigned a 16-bit address within the
address range of the 8085.
The exchange of data with these devices follows
the transfer of data with memory. The user uses
the same instructions used for memory.
3

IO Mapped IO
It treats them separately from memory.
I/O devices are assigned a port number within
the 8-bit address range of 00H to FFH.
The user in this case would access these devices
using the IN and OUT instructions only.

IO mapped IO V/s Memory Mapped IO


Memory Mapped IO

IO is treated as
memory.
16-bit addressing.
More Decoder
Hardware.
Can address 216=64k
locations.
Less memory is
available.

IO Mapped IO

IO is treated IO.
8- bit addressing.
Less Decoder Hardware.
Can address 28=256
locations.
Whole memory address
space is available.
5

IO mapped IO V/s Memory Mapped


IO
Memory Mapped IO Mapped IO
IO
Memory Instructions Special Instructions
are used.
Memory control
signals are used.
Arithmetic and logic
operations can be
performed on data.
Data transfer b/w
register and IO.

are used like IN,


OUT.
Special control
signals are used.
Arithmetic and logic
operations can not
be performed on
data.
Data transfer6 b/w

The interfacing of output devices


Output devices are usually slow.
Also, the output is usually expected to continue
appearing on the output device for a long period
of time.
Given that the data will only be present on the
data lines for a very short period (microseconds),
it has to be latched externally.

The interfacing of output devices


To do this the external latch should be
enabled when the ports address is present
on the address bus, the IO/M signal is set
high and WR is set low.
The resulting signal would be active when
the output device is being accessed by the
microprocessor.
Decoding the address bus (for memorymapped devices) follows the same
techniques discussed in interfacing memory.

Interfacing of Input Devices


The basic concepts are similar to interfacing of
output devices.
The address lines are decoded to generate a signal
that is active when the particular port is being
accessed.
An IORD signal is generated by combining the
IO/M and the RD signals from the microprocessor.

Interfacing of Input Devices


A tri-state buffer is used to connect the input
device to the data bus.
The control (Enable) for these buffers is connected
to the result of combining the address signal and
the signal IORD.

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