295 60229 Verilog Tutorial1
295 60229 Verilog Tutorial1
VERILOG HDL
Basic Unit A module
Module
Describes the functionality of the design
States the input and output ports
Example: A Computer
Functionality: Perform user defined computations
I/O Ports: Keyboard, Mouse, Monitor, Printer
Module
General definition
Example
variable declaration;
description of behavior
endmodule
Lexical Conventions
Comments
// Single line comment
/* Another single line comment */
/* Begins multi-line (block) comment
All text within is ignored
Line below ends multi-line comment
*/
Number
decimal, hex, octal, binary
unsized decimal form
size base form
include underlines, +,-
String
" Enclose between quotes on a single line"
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Description Styles
Structural: Logic is described in terms of Verilog
gate primitives
Example:
not n1(sel_n, sel);
and a1(sel_b, b, sel_b);
and a2(sel_a, a, sel);
or o1(out, sel_b, sel_a);
b
sel
n1
a1
sel_b
sel_n
o1
a
a2
out
sel_a
sel_b
sel_n
out
sel_a
a
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Black Box
2x1 MUX
out
sel
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Structural Modeling
Execution: Concurrent
Format (Primitive Gates):
and G2(Carry, A, B);
Dataflow Modeling
Uses continuous assignment statement
Format: assign [ delay ] net = expression;
Example: assign sum = a ^ b;
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Timescale
`timescale 1ns/100ps
1 Time unit = 1 ns
Time precision is 100ps (0.1 ns)
10.512ns is interpreted as 10.5ns
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Behavioral Modeling
Example:
module mux_2x1(a, b, sel, out);
input a, a, sel;
output out;
always @(a or b or sel)
begin
if (sel == 1)
out = a;
else out = b;
end
endmodule
Sensitivity List
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Sum = A ^ B;
#2 Carry = A & B;
Delayed execution
Intra-Assignment Delay
Example:
Sum = A ^ B;
Carry = #2 A & B;
Delayed assignment
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Procedural Constructs
Two Procedural Constructs
initial Statement
always Statement
initial begin
Sum = 0;
Carry = 0;
end
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Event Control
Event Control
Edge Triggered Event Control
Level Triggered Event Control
Edge Triggered Event Control
@ (posedge CLK) //Positive Edge of CLK
Curr_State = Next_state;
Loop Statements
Loop Statements
Repeat
While
For
Repeat Loop
Example:
repeat (Count)
sum = sum + 5;
If condition is a x or z it is treated as 0
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If condition is a x or z it is treated as 0
For Loop
Example:
for (Count = 0; Count < 10; Count = Count + 1) begin
sum = sum + 5;
end
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Conditional Statements
if Statement
Format:
if (condition)
procedural_statement
else if (condition)
procedural_statement
else
procedural_statement
Example:
if (Clk)
Q = 0;
else
Q = D;
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Example 2:
case (3b101 << 2)
3b100: A = B + C;
4b0100: A = B C;
5b10100: A = B / C; //This statement is
executed
endcase
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Data Types
Net Types: Physical Connection between structural
elements
Register Type: Represents an abstract storage
element.
Default Values
Net Types : z
Register Type : x
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Data Types
Net Type: Wire
wire [ msb : lsb ] wire1, wire2,
Example
wire Reset; // A 1-bit wire
wire [6:0] Clear; // A 7-bit wire
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Behavioral Modeling
Can use only reg data type (within initial and always
constructs)
Cannot use wire data type
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Memories
An array of registers
reg [ msb : lsb ] memory1 [ upper : lower ];
Example
reg [ 0 : 3 ] mem [ 0 : 63 ];
// An array of 64 4-bit registers
reg mem [ 0 : 4 ];
// An array of 5 1-bit registers
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Compiler Directives
`define (Similar to #define in C) used to define
global parameter
Example:
`define BUS_WIDTH 16
reg [ `BUS_WIDTH - 1 : 0 ] System_Bus;
`undef BUS_WIDTH
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System Tasks
Display tasks
$display : Displays the entire list at the time when
statement is encountered
$monitor : Whenever there is a change in any
argument, displays the entire list at end of time step
Time
$time: gives the simulation
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parent_mod
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parent_mod
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Test Bench
`timescale 1ns/100ps
module Top;
reg PA, PB;
wire PSum, PCarry;
HalfAdder G1(PA, PB, PSum, PCarry);
initial begin: LABEL
reg [2:0] i;
for (i=0; i<4; i=i+1) begin
{PA, PB} = i;
#5 $display (PA=%b PB=%b PSum=
%b
PCarry=%b, PA, PB, PSum,
PCarry);
end // for
end // initial
endmodule
Test Bench
Apply Inputs
Design
Module
Observe Outputs
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Caution:
Initial value of Clock (wire data
type) = z
~z = x and ~x = x
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initial begin
Clock = 0;
forever loop can
end
also be used to
generate clock
always begin
#10 Clock = ~ Clock;
end
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